NDLI: Dynamic binary translation for accumulator-oriented architectures

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Dynamic binary translation for accumulator-oriented architectures

Content Provider	ACM Digital Library
Author	Kim, Ho-Seop Smith, James E.
Abstract	A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set that exposes instruction dependence chains (strands) to a distributed microarchitecture containing a simple instruction pipeline. To support conventional program binaries, a source instruction set (Alpha in our study) is dynamically translated to the target accumulator instruction set. The binary translator identifies chains of inter-instruction dependences and assigns them to dependence-carrying accumulators. Because the underlying superscalar microarchitecture is capable of dynamic instruction scheduling, the binary translation system does not perform aggressive optimizations or re-schedule code; this significantly reduces binary translation overhead.Detailed timing simulation of the dynamically translated code running on an accumulator-based distributed microarchitecture shows the overall system is capable of achieving similar performance to an ideal out-of-order superscalar processor, ignoring the significant clock frequency advantages that the accumulator-based hardware is likely to have. As part of the study, we evaluate an instruction set modification that simplifies precise trap implementation. This approach significantly reduces the number of instructions required for register state copying, thereby improving performance. We also observe that translation chaining methods can have substantial impact on the performance, and we evaluate a number of chaining methods.
Starting Page	25
Ending Page	35
Page Count	11
File Format	PDF
ISBN	076951913X
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-03-23
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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