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  1. Proceedings of the 4th International Workshop on Energy Efficient Supercomputing (E2SC '16)
  2. Quantifying energy use in dense shared memory HPC node
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Power-constrained performance scheduling of data parallel tasks
Economic viability of hardware overprovisioning in power-constrained high performance computing
Quantifying energy use in dense shared memory HPC node
A unified platform for exploring power management strategies
An ECM-based energy-efficiency optimization approach for bandwidth-limited streaming kernels on recent Intel Xeon processors
Runtime power limiting of parallel applications on Intel Xeon Phi processors
Characterizing power and performance of GPU memory access
Preliminary investigation of mobile system features potentially relevant to HPC
Energy aware scheduling study on BlueWonder
Software controlled clock modulation for energy efficiency optimization on Intel processors
Neural network-based task scheduling with preemptive fan control

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Quantifying energy use in dense shared memory HPC node

Content Provider ACM Digital Library
Author Manne, Srilatha GalOn, Shay Ono, Makoto Puzović, Miloš
Abstract In this paper we introduce a novel, dense, system-on-chip many-core Lenovo NeXtScale $System^{®}$ server based on the Cavium $ThunderX^{®}$ ARMv8 processor that was designed for performance, energy efficiency and programmability. ThunderX processor was designed to scale up to 96 cores in a cache coherent, shared memory architecture. Furthermore, this hardware system has a power interface board (PIB) that measures with high accuracy power draw across the server board in the NeXtScale™ chassis. We use data obtainable from PIB to measure the energy use of PARSEC and Splash-2 benchmarks and demonstrate how to use available hardware counters from ThunderX processor in order to quantify the amount of energy that is used by different aspects of shared memory programming, such as cache coherent communication. We show that energy used required to keep caches coherent is negligible and demonstrate that shared memory programming paradigm is viable candidate for future energy aware HPC designs.
Starting Page 16
Ending Page 23
Page Count 8
File Format PDF
ISBN 9781509038565
DOI 10.1109/E2SC.2016.7
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2016-11-13
Access Restriction Subscribed
Subject Keyword Measurement Accuracy High performance computing High density Energy efficiency Power monitoring System-on-chip Manycore
Content Type Text
Resource Type Article
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