NDLI: A low cost hardware oriented motion estimation algorithm for HDTV

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A low cost hardware oriented motion estimation algorithm for HDTV

Content Provider	ACM Digital Library
Author	Zhang, Zhangyao Teng, Guowei Wang, He Wang, Guozhong
Abstract	A hardware oriented Motion Estimation (ME) algorithm which can be combined into FPGA based SDTV or HDTV encoder is proposed. The present Full Search (FS) algorithm cost too much logic resource, thus it limits the application of real time video encoder. And all of the fast algorithms are difficult to reuse data between candidates, thus they are not suitable for ASIC or FPGA implementation. After reviewing the previous ME algorithms and researching the distribution of Motion Vector (MV), we optimize the hardware ME by selecting block-matching candidates in the Search Window (SW). Then a novel Big-Hexagon-Like searching route is proposed. And the number of PE arrays is decreased from 8 to 2. Therefore, the high logic resource cost of ME is alleviated notably. And the method of data reusing is also proposed. Then a hardware architecture is proposed. We have tested the proposal with High definition, CIF and QCIF video sequences. Comparing the test result with F017 and Diamond algorithms, the proposal has a comparative RDO (Rate-Distortion Optimization) performance to F017 and is better than Diamond which is adopted by T264. An FPGA implementation of the proposed algorithm is realized, the result of implementation shows that the equivalent gates count is reduced to 121K.
Starting Page	529
Ending Page	536
Page Count	8
File Format	PDF
ISBN	9781605583266
DOI	10.1145/1543834.1543906
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2009-06-12
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Motion estimation Low cost Hardware oriented algorithm Rdo
Content Type	Text
Resource Type	Article

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