NDLI: The Java Virtual Machine in retargetable, high-performance instruction set simulation

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The Java Virtual Machine in retargetable, high-performance instruction set simulation

Content Provider	ACM Digital Library
Author	Häsing, Matthias Preußer, Thomas Spallek, Rainer Kaufmann, Marco
Abstract	Two main demands on instruction set simulation are portability and high simulation performance. For the testing and benchmarking of ISA prototypes such as in an ASIP design process, simulators are additionally required to offer retargetability for the rapid modeling and revisal of their simulation targets. In this paper, we present the techniques applied in a full-system instruction set simulation framework that combines these three conflicting demands. Our framework is retargetable, portable and provides high simulation performance. It is entirely implemented in Java and features a two-stage dynamic binary translation (DBT) targeting Java Bytecode in the first stage and employing the Java Virtual Machine as an external code generation back end in the second stage. While the use of state-of-the-art techniques such as DBT generates high simulation performance, the framework is also platform independent and can run on any J2SE-compliant Java Runtime Environment. In spite of this platform independence, the native code generated in the second stage will even profit from the platform-specific optimizations performed by modern JVM implementations. Our second contribution is HPADL, the instruction set description language that provides the retargetability of our framework. HPADL is tailored for the specific needs of dynamically compiling full-system IS simulation. Due to its clean separation of concerns between the instruction decoding and instruction execution, it easily enables DBT. Also, it is not restricted to a specific range of target architectures such as RISC. In this paper, we will compare the modeling effort in HPADL to that of QEMU. For our experiments and in order to show the practicability and flexibility of our approach, we implemented HPADL models of the DLX, 8086, ARMv4 and PowerPC/PowerPC VLE ISA as well as some IO device models in Java. A comparison with the simulation performance of QEMU by reference of the EEMBC AutoBench 1.1 shows that we achieve 78% of the QEMU performance on average.
Starting Page	21
Ending Page	30
Page Count	10
File Format	PDF
ISBN	9781450309356
DOI	10.1145/2093157.2093161
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2011-08-24
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Instruction set simulation Java Retargetable Dynamic binary translation Virtualization
Content Type	Text
Resource Type	Article

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