NDLI: PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions

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Towards automated ECOs in FPGAs

Architectural enhancements in Stratix-III™ and Stratix-IV™

A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation

FPGA-based front-end electronics for positron emission tomography

CMOS vs Nano: comrades or rivals?

Making good points: application-specific pareto-point generation for design space exploration using statistical methods

FPCNA: a field programmable carbon nanotube array

SPR: an architecture-adaptive CGRA mapping tool

Large-scale wire-speed packet classification on FPGAs

SmartOpt: an industrial strength framework for logic synthesis

A high performance fpga-based implementation of position specific iterated blast

HW/SW methodologies for synchronization in FPGA multiprocessors

Soft vector processors vs FPGA custom hardware: measuring and reducing the gap

Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller

A parallel/vectorized double-precision exponential core to accelerate computational science applications

Emerging application domains: research challenges and opportunities for FPGAs

Clock power reduction for virtex-5 FPGAs

Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs

A high-performance FPGA architecture for restricted boltzmann machines

Fpga-based face detection system using Haar classifiers

VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling

Flexible multi-mode embedded floating-point unit for field programmable gate arrays

Synthesis of reconfigurable high-performance multicore systems

Fast and scalable packet classification using perfect hash functions

Cholesky decomposition using fused datapath synthesis

A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs

Automatic bus macro placement for partially reconfigurable FPGA designs

Data streaming and simd support for the microblaze architecture

Performance and power of cache-based reconfigurable computing

FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis

Choose-your-own-adventure routing: lightweight load-time defect avoidance

A comparison of via-programmable gate array logic cell circuits

A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer

A 17ps time-to-digital converter implemented in 65nm FPGA technology

FPGA technology mapping with encoded libraries andstaged priority cuts

Wirelength modeling for homogeneous and heterogeneous FPGA architectural development

Intel® atom™ processor core made FPGA-synthesizable

Diagonal tracks in FPGAs: a performance evaluation

PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions

Bus mastering PCI express in an FPGA

Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation

Computation reuse in domain-specific optimization of signal recognition

A novel BIST approach for testing input/output buffers in FPGAs

Scalable don't-care-based logic optimization and resynthesis

High-performance, energy-efficient platforms using in-socket FPGA accelerators

Customizable bit-width in an OpenMP-based circuit design tool

The input-aware dynamic adaptation of area and performance for reconfigurable accelerator

Impact and compensation of correlated process variation on ring oscillator based puf

Revisiting bitwidth optimizations

Implementation of the reconfiguration port scheduling on the erlangen slot machine

A novel minloop SB design to improve FPGA routability

A clustering framework for task partitioning based on function-level data usage analysis

HMMer acceleration using systolic array based reconfigurable architecture

High-performance, cost-effective heterogeneous 3D FPGA architectures

An intermediate hardware model with load/store unit for C to FPGA

FPGA implementation of real-time skin color detection with mean-based surface flattening

Measuring and modeling variabilityusing low-cost FPGAs

N-port memory mapping for LUT-based FPGAs

Streaming implementation of a sequential decompression algorithm on an FPGA

3D configuration caching for 2D FPGAs

Parallel placement for FPGAs revisited

32-bit floating-point FPGA gaussian elimination

Implementation of a genetic algorithm on a virtex-ii pro FPGA

Closed-loop modeling of power and temperature profiles of FPGAs

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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