NDLI: An accurate functional level concurrent fault simulator

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Chairman's introduction

Keynote speaker

The evolution of design automation to meet the challanges of VLSI

A generalized channel router

A “grid-free” channel router

An over-the-cell router

Design automation at a large architect-engineer

System facilities for CAD databases

Weaknesses of commercial data base management systems in engineering applications

A new test pattern generation system

Fault diagnosis based on effect-cause analysis: An introduction

Test generation costs analysis and projections

Issues in IC implementation of high level, abstract designs

A layout system for the random logic portion of MOS LSI

Automation of design for uncommitted logic array

The standard transistor array (STAR): Part I A two-layer metal semicustom design system

Inter-active graphic methods for automating mechanical engineering design and analyses

Computer-aided assignment of manufacturing tolerances

Automation of sheet metal design and manufacturing

Verification of timing constraints on large digital systems

The SLIDE simulator: A facility for the design and analysis of computer interconnections

Developments in verification of design correctness (A Tutorial)

A survey of space allocation algorithms in use in architectural design in the past twenty years

Digital test generation and design for testability

SCOAP: Sandia controllability/observability analysis program

The design and implementation of fault insertion capabilities for ISPS

An accurate functional level concurrent fault simulator

An integrated CAD system for architecture

A prestructuring model for system arrangement problems

A data structure for interactive placement of rectangular objects

A line-expansion algorithm for the general routing problem with a guaranteed solution

A fast maze router with iterative use of variable search space restriction

An implementation of a saturated zone multi-layer printed circuit board router

Design integrity and immunity checking: A new look at layout verification and design rule checking

A hierarchical approach for layout versus circuit consistency check

A hierarchical approach for layout versus circuit consistency check

An integrated mask artwork analysis system

An IC design station needs a high performance color graphic display

SIDS (A Symbolic Interactive Design System)

Interactive wiring system

Optimization of the influence of problem modifications on given microprogrammed controllers

Alex: A conversational, hierarchical logic design system

Verifying deep logic hierarchies with ALEX

Design automation and VLSI in the 80's (Panel Discussion)

A contemporary perspective on design automation and VLSI in the 80's (Position Statement)

Design automation trends for VLSI in the 1980s (Position Statement)

Design automation and VLSI in the 80's (Position Statement)

Design tools for VLSI (Position Statement)

The VLSI design challenge of the 80's (Position Statement)

VLSI - a challenge for system designers (Position Statement)

Desisn automation and VLSI in the 80's (Position Statement)

The management of engineering changes using the PRIMUS system

An interactive test data system for LSI production testing

A tool to support design automation in batch manufacturing

High-speed concurrent fault simulation with vectors and scalars

An optimized ATPG

Methods for generalized deductive fault simulation

The incorporation of functional level element routines into an existing digital simulation system

The complexity of design automation problems

Complexity theory and design automation

Design process analysis: A measurement and analysis technique

The electronics engineer's design station

An Interactive Graphics System for custom design

Technical documentation by “MAGIC” (Machine Aided Graphics for Illustration and Composition

The use of graphics processors for circuit design simulation at GTE AE Labs

The Standard Transistor Array (star) (Part II automatic cell placement techniques)

Efficient placement and routing techniques for master slice LSI

Comet - a fast component placer

Gate assignment and pack placement: Two approaches compared

Algebraic analysis of nondeterministic behavior

Detecting bridging and stuck-at faults at input and output pins of standard digital components

Automatic design with dependence graphs

The real world of design automation - part III or The user's viewpoint chairman's introduction (Panel Discussion)

A CAD user's perspective what gets done right wrong and not at all (Position Paper)

Will your bridge stand the load? (Position Paper)

Observations of a CAD user (Position Paper)

An automatic routing system for high density multilayer printed wiring boards

The interchange algorithms for circuit placement problems

The genealogical approach to the layout problem

A new look at logic synthesis

Combinational logic synthesis from an HDL description

Practical automated design of LSI for large computers

Table lookup techniques for fast and flexible digital logic simulation

Justification and financial analysis for CAD

A prototyping and simulation approach to interactive computer system design

Selecting and successfully implementing a turnkey computer graphics system

A hierarchical bit-map format for the representation of IC mask data

Cell map representation for hierarchical layout

SLIM-the translation of symbolic layouts into mask data

A data structure for gridless routing

A multiple delay simulator for MOS LSI circuits

A mixed-mode simulator

MIXS: A mixed level simulator for large digital system logic verification

Functional level simulation at Raytheon

Position statement - CAD for VLSI

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in