NDLI: Cell GC: using the cell synergistic processor as a garbage collection coprocessor

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Cell GC: using the cell synergistic processor as a garbage collection coprocessor

Content Provider	ACM Digital Library
Author	Gschwind, Michael Cher, Chen-Yong
Abstract	In recent years, scaling of single-core superscalar processor performance has slowed due to complexity and power considerations. To improve program performance, designs are increasingly adopting chip multiprocessing with homogeneous or heterogeneous CMPs. By trading off features from a modern aggressive superscalar core, CMPs often offer better scaling characteristics in terms of aggregate performance, complexity and power, but often require additional software investment to rewrite, retune or recompile programs to take advantage of the new designs. The Cell Broadband Engine is a modern example of a heterogeneous CMP with coprocessors (accelerators) which can be found in supercomputers (Roadrunner), blade servers (IBM QS20/21), and video game consoles (SCEI PS3). A Cell BE processor has a host Power RISC processor (PPE) and eight Synergistic Processor Elements (SPE), each consisting of a Synergistic Processor Unit (SPU) and Memory Flow Controller (MFC). In this work, we explore the idea of offloading Automatic Dynamic Garbage Collection (GC) from the host processor onto accelerator processors using the coprocessor paradigm. Offloading part or all of GC to a coprocessor offers potential performance benefits, because while the coprocessor is running GC, the host processor can continue running other independent, more general computations. . We implement BDW garbage collection on a Cell system and offload the mark phase to the SPE co-processor. We show mark phase execution on the SPE accelerator to be competitive with execution on a full fledged PPE processor. We also explore object-based and block-based caching strategies for explicitly managed memory hierarchies, and explore to effectiveness of several prefetching schemes in the context of garbage collection. Finally, we implement Capitulative Loads using the DMA by extending software caches and quantify its performance impact on the coprocessor.
Starting Page	141
Ending Page	150
Page Count	10
File Format	PDF
ISBN	9781595937964
DOI	10.1145/1346256.1346276
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2008-03-05
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Garbage collection Mark-sweep Local store Bdw Coprocessor Spe Spu Explicitly managed memory hierarchies Cell Accelerator
Content Type	Text
Resource Type	Article

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