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  1. Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (MSPC '13)
  2. Cache rationing for multicore
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APE: accelerator processor extensions to optimize data-compute co-location
A study of data structures with a deep heap shape
A low overhead method for recovering unused memory inside regions
Program-centric cost models for locality
Introducing kernel-level page reuse for high performance computing
Software-controlled transparent management of heterogeneous memory resources in virtualized systems
A new perspective on processing-in-memory architecture design
A coldness metric for cache optimization
All-window data liveness
Software-level scheduling to exploit non-uniformly shared data cache on GPGPU
Cache rationing for multicore
Analyzing locality of memory references in GPU architectures

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Cache rationing for multicore

Content Provider ACM Digital Library
Author Brock, Jacob Ding, Chen
Abstract As the number of transistors on a chip increases, they are used mainly in two ways on multicore processors: first, to increase the number of cores, and second, to increase the size of cache memory. The two approaches intersect at a basic problem, which is how parallel tasks can best share the cache memory. The degree of sharing determines the available cache resource for each core and hence the memory performance and scalability of the system. In this paper, cache rationing is presented as a cache sharing solution for collaborative caching.
Starting Page 1
Ending Page 2
Page Count 2
File Format PDF
ISBN 9781450321037
DOI 10.1145/2492408.2492422
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2013-06-16
Publisher Place New York
Access Restriction Subscribed
Subject Keyword Cache replacement policy Cache sharing Collaborative caching
Content Type Text
Resource Type Article
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