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  1. Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware (HWWS '05)
  2. Fully procedural graphics
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GPU-accelerated high-quality hidden surface removal
Hexagonal storage scheme for interleaved frame buffers and textures
Hardware-compatible vertex compression using quantization and simplification
Optimal automatic multi-pass shader partitioning by dynamic programming
KD-tree acceleration structures for a GPU raytracer
A fast, energy-efficient z-comparator
iPACKMAN: high-quality, low-complexity texture compression for mobile phones
Generic mesh refinement on GPU
Split-plane shadow volumes
A hardware architecture for multi-resolution volume rendering
A reconfigurable architecture for load-balanced rendering
Modified noise for evaluation on graphics hardware
Fully procedural graphics

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Fully procedural graphics

Content Provider ACM Digital Library
Author Kajiya, J. Whitted, T.
Abstract The growing application of user-defined programs within graphics processing units (GPUs) has transformed the fixed-function display pipeline into a largely programmable pipeline. In this paper we propose that the elements fed through the pipeline be made entirely procedural. To enable this, we present a modification of the conventional graphics processor in which all procedures are executed in a common processor array and the rasterizer is augmented with a more general sampling controller. By executing both the geometric and shading elements of a procedural graphics model in a single processor we retain the data amplification that distinguishes procedural descriptions without a corresponding explosion of external bandwidth.
Starting Page 81
Ending Page 90
Page Count 10
File Format PDF
ISBN 1595930868
DOI 10.1145/1071866.1071879
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2005-07-30
Publisher Place New York
Access Restriction Subscribed
Content Type Text
Resource Type Article
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