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  1. Proceedings of the 9th Annual Workshop on General Purpose Processing using Graphics Processing Unit (GPGPU '16)
  2. Runtime aware architectures
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Runtime aware architectures
Performance portable GPU code generation for matrix multiplication
Working together to build the heterogeneous processing ecosystem
A systems perspective on GPU computing: a tribute to Karsten Schwan
GPU centric extensions for parallel strongly connected components computation
Multi-stage programming for GPUs in C++ using PACXX
Implementing directed acyclic graphs with the heterogeneous system architecture
Designing high performance communication runtime for GPU managed memory: early experiences
General-purpose join algorithms for large graph triangle listing on heterogeneous systems
Simplifying programming and load balancing of data parallel applications on heterogeneous systems
GPUpIO: the case for I/O-driven preemption on GPUs
Effective resource management for enhancing performance of 2D and 3D stencils on GPUs

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Runtime aware architectures

Content Provider ACM Digital Library
Author Valero, Mateo
Abstract In the last years the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore's Law vanished. When uni-cores were the norm, hardware design was decoupled from the software stack thanks to a well defined Instruction Set Architecture (ISA). This simple interface allowed developing applications without worrying too much about the underlying hardware, while computer architects proposed techniques to aggressively exploit Instruction-Level Parallelism (ILP) in superscalar processors. Current multi-cores are designed as simple symmetric multiprocessors on a chip. While these designs are able to compensate the clock frequency stagnation, they face multiple problems in terms of power consumption, programmability, resilience or memory. The solution is to give more responsibility to the runtime system and to let it tightly collaborate with the hardware. The runtime has to drive the design of future multi-cores architectures. In this talk, we introduce an approach towards a Runtime-Aware Architecture (RAA), a massively parallel architecture designed from the runtime's perspective.
Starting Page 1
Ending Page 1
Page Count 1
ISBN 9781450341950
DOI 10.1145/2884045.2884055
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2016-03-12
Publisher Place New York
Access Restriction Subscribed
Content Type Text
Resource Type Article
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