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  1. Proceedings of the Third Conference on Partitioned Global Address Space Programing Models (PGAS '09)
  2. ScaleUPC: a UPC compiler for multi-core systems
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Computational science and engineering requirements for new languages: the need and the barriers
Coarrays in Fortran 2008
A new vision for coarray Fortran
A practical study of UPC using the NAS Parallel Benchmarks
A simple parallel approximation algorithm for maximum weight matching
Beyond UPC
A comparative study and empirical evaluation of global view High performance Linpack program in X10
UPC performance evaluation on a multicore system
Fast PGAS connected components algorithms
Shared memory programming on distributed memory systems
Evaluating error detection capabilities of UPC run-time systems
Evaluation of UPC programmability using classroom studies
ScaleUPC: a UPC compiler for multi-core systems

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ScaleUPC: a UPC compiler for multi-core systems

Content Provider ACM Digital Library
Author Zhao, Weiming Wang, Zhenlin
Abstract Since multi-core computers began to dominate the market, enormous efforts have been spent on developing parallel programming languages and/or their compilers to target this architecture. Although Unified Parallel C (UPC), a parallel extension to ANSI C, was originally designed for large scale parallel computers and cluster environments, its partitioned global address space programming model makes it a natural choice for a single multi-core machine, where the main memory is physically shared. This paper builds a case for UPC as a feasible language for multi-core programming by providing an optimizing compiler, called ScaleUPC, which outperforms other UPC compilers targeting SMPs. As the communication cost for remote accesses is removed because all accesses are physically local in a multi-core, we find that the overhead of pointer arithmetic on shared data accesses becomes a prominent bottleneck. The reason is that directly mapping the UPC logical memory layout to physical memory, as used in most of the existing UPC compilers, incurs prohibitive address calculation overhead. This paper presents an alternative memory layout, which effectively eliminates the overhead without sacrificing the UPC memory semantics. Our research also reveals that the compiler for multi-core systems needs to pay special attention to the memory system. We demonstrate how the compiler can enforce static process/thread binding to improve cache performance.
Starting Page 1
Ending Page 8
Page Count 8
File Format PDF
ISBN 9781605588360
DOI 10.1145/1809961.1809976
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2009-10-05
Publisher Place New York
Access Restriction Subscribed
Content Type Text
Resource Type Article
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