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| Content Provider | ACM Digital Library |
|---|---|
| Author | Das, Shirshendu Kapoor, Hemangee K. Chakraborty, Shounak |
| Abstract | With the rapid growth in semiconductor technology, modern processor chips have multiple number of processor cores with multi-level on-chip caches. Recent study about the chip power consumption indicates that, the principal amount of chip power is consumed by the on chip caches which can be divided into two major parts: dynamic power and static power. Dynamic power is consumed when the cache is accessed and static power is generally referred as leakage power of the cache. This increased power consumption of chip increases chip-temperature which increases on chip leakage power. In this paper we attempt to reduce the static power consumption by intelligently powering off cache banks and mapping its requests to other active cache banks. We use a performance based criteria for the shutdown decision and the bank to be powered off is chosen based on usage statistics. The remapping of requests for a powered off cache bank is done at the L2-controller and thus the L1 caches are transparent to this approach. Thus, depending on the applications workload and data distribution, a controlled number of banks can be dynamically shutdown saving on the leakage power dissipation. Experimental analysis shows 43% reduction in static power and 19% reduction in EDP. |
| Starting Page | 1913 |
| Ending Page | 1918 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781450331968 |
| DOI | 10.1145/2695664.2695763 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2015-04-13 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Subject Keyword | Chip multiprocessor Last level cache Power optimisation Dynamic power Performance Leakage power |
| Content Type | Text |
| Resource Type | Article |
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