NDLI: PMA: Pixel-based multi-anchor algorithm for image recognition on multi-core systems

Please wait, while we are loading the content...

Kokkos Array performance-portable manycore programming model

AGC: adaptive global clock in software transactional memory

GHOST: GPGPU-offloaded high performance storage I/O deduplication for primary storage system

Efficient execution of time-step computations with pipelined parallelism and inter-thread data locality optimizaitions

PMA: Pixel-based multi-anchor algorithm for image recognition on multi-core systems

Revisiting shared virtual memory systems for non-coherent memory-coupled cores

An hybrid model for very high level threads

Exploring parallelism in volume ray casting: understanding the programming issues of multithreaded accelerators

Function flow: making synchronization easier in task parallelism

Efficient memory management of a hierarchical and a hybrid main memory for MN-MATE platform

New strategy for coarse grid solvers in parallel multigrid methods using OpenMP/MPI hybrid programming models

Better speedups using simpler parallel programming for graph connectivity and biconnectivity

Massively parallel breadth first search using a tree-structured memory model

Shared work list: hacking amorphous data parallelism in UPC

A case for secure and scalable hypervisor using safe language

Techniques for the parallelization of unstructured grid applications on multi-GPU systems

Semi-sparse algorithm based on multi-layer optimization for recommendation system

Chestnut: a GPU programming language for non-experts

Networks beat pipelines: the design of FG 2.0

PMA: Pixel-based multi-anchor algorithm for image recognition on multi-core systems

Content Provider	ACM Digital Library
Author	Guo, Minyi Tang, Xiaoxin Shen, Yao Li, Li Zheng, Long Ma, Jun
Abstract	Image recognition is a very useful technique that can be applied in many areas. Two-Dimensional Continuous Dynamic Programming (2DCDP) is a pixel-level matching algorithm for object recognition. Compared with other methods, 2DCDP can offer a sufficiently high accuracy of recognition without training. In our previous work we use 2DCDP to implement image classification. However, we find the processing speed of 2DCDP is very slow. In this paper, we first analyze the performance issue of 2DCDP algorithm, and point out that large memory consumption is the performance bottleneck. Then, we improve 2DCDP algorithm and propose a new object recognition algorithm named Pixel-based Multi-Anchor (PMA) algorithm, which can locate anchor points that can be further used to locate the recognized area. Theoretical analysis expresses that our new algorithm can effectively reduce memory capacity requirement from $O(n^{4})$ to $O(n^{3}),$ where n is the size of image. Furthermore, based on the understanding of multi-core architecture, we propose a fine-grained parallelism thread model to parallelize our PMA algorithm on mutli-core systems. Especially we take cache coherence problem into account, such that we further propose a coarse-grained parallelism thread model to optimize the PMA performance. Experimental results show that compared with the original 2DCDP algorithm, our new PMA algorithm can decrease the memory capacity requirement dramatically which improves the recognition speed. More important, PMA algorithm can processes efficiently big images that exceed the ability of original 2DCDP algorithm.
Starting Page	36
Ending Page	44
Page Count	9
File Format	PDF
ISBN	9781450312110
DOI	10.1145/2141702.2141707
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2012-02-26
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Image recognition Chip multiprocessor Pixel-based matching
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in