NDLI: SystemC and SystemVerilog: Where do They Fit? Where are They Going?

Please wait, while we are loading the content...

Opportunities and Challenges in Building Silicon Products in 65nm and Beyond

Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times

Hybrid Architectural Dynamic Thermal Management

Value-Conscious Cache: Simple Technique for Reducing Cache Access Power

State-Preserving vs. Non-State-Preserving Leakage Control in Caches

Arithmetic Reasoning in DPLL-Based SAT Solving

Enhanced Diameter Bounding via Structural

Improved Symoblic Simulation by Dynamic Funtional Space Partitioning

Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults

Level of Similarity: A Metric for Fault Collapsing

Design of Routing-Constrained Low Power Scan Chains

Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis

A 2.7V 350µW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed Inputs

Digital Background Gain Error Correction in Pipeline ADCs

Digital Ground Bounce Reduction by Phase Modulation of the Clock

Pseudo-Random Sequence Based Tuning System for Continuous-Time Filters

A Crosstalk Aware Interconnect with Variable Cycle Transmission

Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip

Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow

SystemC and SystemVerilog: Where do They Fit? Where are They Going?

Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus

Hierarchical Adaptive Dynamic Power Management

A Self-Tuning Cache Architecture for Embedded Systems

Scheduling Reusable Instructions for Power Reduction

Using Counter Example Guided Abstraction Refinement to Find Complex Bugs

Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor

Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements

A Probabilistic Method for the Computation of Testability of RTL Constructs

Graph-Based Functional Test Program Generation for Pipelined Processors

Automatic Generation of Validation Stimuli for Application-Specific Processors

Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques

Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies

Automatic Tuning of Two-Level Caches to Embedded Applications

Low Static-Power Frequent-Value Data Caches

Using a Victim Buffer in an Application-Specific Memory Hierarchy

High Security Smartcards

Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints

A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations

A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation

Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling

Managing Don't Cares in Boolean Satisfiability

Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors

A Novel SAT All-Solutions Solver for Efficient Preimage Computation

Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and Benefits

Random Jitter Extraction Technique in a Multi-Gigahertz Signal

Low Cost Analog Testing of RF Signal Paths

A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications

A Novel Implementation of Tile-Based Address Mapping

Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks

Time-Energy Design Space Exploration for Multi-Layer Memory Architectures

Breaking Instance-Independent Symmetries in Exact Graph Coloring

How Can System-Level Design Solve the Interconnect Technology Scaling Problem?

System Design Using Kahn Process Networks: The Compaan/Laura Approach

Microarchitecture Development via Metropolis Successive Platform Refinement

Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design

SoftContract: an Assertion-Based Software Development Process that Enables Design-by-Contract

A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors

Refinement of Mixed-Signal Systems with Affine Arithmetic

System-Level Performance Analysis in SystemC

Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks

Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures

Aspects of Formal and Graphical Design of a Bus System

Scan Power Minimization through Stimulus and Response Transformations

Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC's

Wrapper Design for Testing IP Cores with Multiple Clock Domains

Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures

An Arithmetic Structure for Test Data Horizontal Compression

A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design

Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques

Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines

Extended Subspace Identification of Improper Linear Systems

Identification and Modeling of Nonlinear Dynamic Behavior in Analog Circuits

Exploring Logic Block Granularity for Regular Fabrics

Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures

A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning

Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms

Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization

A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks

Impact of Data Transformations on Memory Bank Locality

Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work

Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems

Dynamic Power Management Using Data Buffers

Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications

High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study

A SystemC-Based Verification Methodology for Complex Wireless Software IP

A New Optimized Implemention of the SystemC Engine Using Acyclic Scheduling

Stimuli Generation with Late Binding of Values

Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC

Extraction of Schematic Array Models for Memory Circuits

Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors

Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA

Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow

On Concurrent Error Detection with Bounded Latency in FSMs

Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models

Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis

SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level

Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming

System Design for DSP Applications Using the MASIC Methodology

Flexible Software Protection Using Hardware/Software Codesign Techniques

Interactive Cosimulation with Partial Evaluation

Communication Analysis for System-On-Chip Design

Extremely Low-Power Logic

Decomposition of Instruction Decoder for Low Power Design

Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors

Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent?

Functional Coverage Metric Generation from Temporal Event Relation Graph

Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits

Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] Modulators

A Methodology for System-Level Analog Design Space Exploration

Systematic Design for Optimization of High-Resolution Pipelined ADCs

A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit

Co-Processor Synthesis: A New Methodology for Embedded Software Acceleration

Behavioural Bitwise Scheduling Based on Computational Effort Balancing

A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters

On Transfer Function and Power Consumption Transient Response

Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits

Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation

A Game Theoretic Approach to Low Energy Wireless Video Streaming

Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning

Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC

A Low Power Strategy for Future Mobile Terminals

Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis

A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns

A Digital Test for First-Order [Sigma-Delta] Modulators

SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance

STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores

Are Our Design for Testability Features Fault Secure?

Test Compression and Hardware Decompression for Scan-Based SoCs

Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design

Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating

An Asynchronous Synthesis Toolset Using Verilog

Organizing Libraries of DFG Patterns

Compositional Memory Systems for Data Intensive Applications

Scalar Metric for Temporal Locality and Estimation of Cache Performance

.NET Framework -- A Solution for the Next Generation Tools for System-Level Modeling and Simulation

Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology

Integrating the Synchronous Dataflow Model with UML

Design and Behavioral Modeling Tools for Optical Network-on-Chip

Hierarchical Modeling and Simulation of Large Analog Circuits

Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS

A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement

Enhancing Reliability of Operational Interconnections in FPGAs

Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors

SystemC and SystemVerilog: Where do They Fit? Where are They Going?

Content Provider	ACM Digital Library
Author	Swan, Stuart Martin, Grant Srouji, Johny Sciuto, Donatella Ghenassia, Frank Flake, Peter Rosenstiel, Wolfgang
Abstract	There is tremendous interest in design languages these days - and more particularly, SystemC and SystemVerilog. Sometimes the truth about design languages can be obscured by marketing and the press. This panel is meant to deepen the technical understanding of the DATE audience on the issue of design languages. It contains five technical experts - an academic expert in design languages and SystemC and SystemVerilog in particular; a language expert for each of SystemC and SystemVerilog; and a user expert for these two languages. The language experts have been heavily involved in the specification and evolution of their respective languages. The user experts have been heavily involved in developing use methodologies for these languages within their own design communities, and in applying them to real design problems. The panelists will consider the questions:what are the key capabilities of these languages and what do they offer to users?which design problems are they best used for? what is their scope?how has application of these languages to real design problems improved the productivity of designers and the quality of the design results?where should the languages develop further capabilities?.
File Format	PDF
ISBN	0769520855
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2004-02-16
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in