NDLI: Provably correct high-level timing analysis without path sensitization

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Perturb and simplify: multi-level boolean network optimizer

Multi-level logic optimization by implication analysis

Incremental synthesis

Definition and solution of the memory packing problem for field-programmable systems

Integrating program transformations in the memory-based synthesis of image and video algorithms

Dataflow-driven memory allocation for multi-dimensional signal processing systems

Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation

Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0

Analytical fault modeling and static test generation for analog ICs

Efficient network flow based min-cut balanced partitioning

Multi-way VLSI circuit partitioning based on dual net representation

A general framework for vertex orderings, with applications to netlist clustering

Re-encoding sequential circuits to reduce power dissipation

Precomputation-based sequential logic optimization for low power

Low power state assignment targeting two-and multi-level logic implementations

Algorithm selection: a quantitative computation-intensive optimization approach

Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis

Synthesis of concurrent system interface modules with automatic protocol conversion generation

An efficient procedure for the synthesis of fast self-testable controller structures

Test pattern generation based on arithmetic operations

Random pattern testable logic synthesis

Compression-relaxation: a new approach to performance driven placement for regular architectures

A loosely coupled parallel algorithm for standard cell placement

Delay and area optimization for compact placement by gate resizing and relocation

Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs

A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays

Universal logic gate for FPGA design

Condition graphs for high-quality behavioral synthesis

Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints

Comprehensive lower bound estimation from behavioral descriptions

Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics

VLSI timing simulation with selective dynamic regionization

A new efficient approach to statistical delay modeling of CMOS digital combinational circuits

Simultaneous driver and wire sizing for performance and power optimization

Low-cost single-layer clock trees with exact zero Elmore delay skew

Clock period constrained minimal buffer insertion in clock trees

Efficient implementation of retiming

Retiming with non-zero clock skew, variable register, and interconnect delay

Optimal latch mapping and retiming within a tree

Simulation of digital circuits in the presence of uncertainty

Fast transient power and noise estimation for VLSI circuits

The Inversion Algorithm for digital simulation

Unified complete MOSFET model for analysis of digital and analog circuits

A precorrected-FFT method for capacitance extraction of complicated 3-D structures

Measurement and modeling of MOS transistor current mismatch in analog IC's

Skew sensitivity minimization of buffered clock tree

Process-variation-tolerant clock skew minimization

A specified delay accomplishing clock router using multiple layers

Switching activity analysis considering spatiotemporal correlations

Estimation of circuit activity considering signal correlations and simultaneous switching

A cell-based power estimation in CMOS combinational circuits

Design exploration for high-performance pipelines

Simultaneous functional-unit binding and floorplanning

Module selection and data format conversion for cost-optimal DSP synthesis

On testing delay faults in macro-based combinational circuits

RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults

A comprehensive fault macromodel for opamps

Channel-driven global routing with consistent placement (extended abstract)

A new global routing algorithm for FPGAs

On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution

A symbolic method to reduce power consumption of circuits containing false paths

Multi-level network optimization for low power

LP based cell selection with constraints of timing, area, and power consumption

Power analysis of embedded software: a first step towards software power minimization

Generating instruction sets and microarchitectures from applications

Register assignment through resource classification for ASIP microcode generation

Efficient small-signal circuit analysis and sensitivity computations with the PVL algorithm

Capturing time-of-flight delay for transient analysis based on scattering parameter macromodel

RC interconnect synthesis—a moment fitting approach

Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays

Folding a stack of equal width components

Area minimization for hierarchical floorplans

Multi-level synthesis for safe replaceability

Iterative algorithms for formal verification of embedded real-time systems

Incremental formal design verification

Optimization of critical paths in circuits with level-sensitive latches

Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator

Dynamical identification of critical paths for iterative gate sizing

Built-in self-test and fault diagnosis of fully differential analogue circuits

A new built-in self-test approach for digital-to-analog and analog-to-digital converters

Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring

An enhanced flow model for constraint handling in hierarchical multi-view design environments

On modeling top-down VLSI design

A formal basis for design process planning and management

Design of heterogeneous ICs for mobile and personal communication systems

Embedded systems design for low energy consumption

Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams

Performance-driven synthesis of asynchronous controllers

Decomposition methods for library binding of speed-independent asynchronous designs

On error correction in macro-based circuits

Fault dictionary compaction by output sequence removal

Automatic test program generation for pipelined processors

Synthesis of manufacturable analog circuits

A statistical optimization-based approach for automated sizing of analog cells

Time-domain non-Monte Carlo noise simulation for nonlinear dynamic circuits with arbitrary excitations

Improving over-the-cell channel routing in standard cell design

Minimum crosstalk switchbox routing

Techniques for crosstalk avoidance in the physical design of high-performance digital systems

Efficient breadth-first manipulation of binary decision diagrams

Symmetry detection and dynamic variable ordering of decision diagrams

A redesign technique for combinational circuits based on gate reconnections

Non-scan design-for-testability of RT-level data paths

Selecting partial scan flip-flops for circuit partitioning

Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection

Macromodeling of analog circuits for hierarchical circuit design

Approximate symbolic analysis of large analog integrated circuits

Testing of analog systems using behavioral models and optimal experimental design techniques

Layer assignment for high-performance multi-chip modules

The reproducing placement problem with applications

RISA: accurate and efficient placement routability modeling

A new approach for factorizing FSM's

Boolean constrained encoding: a new formulation and a case study

Optimization of hierarchical designs using partitioning and resynthesis

HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faults

Fast timing simulation of transient faults in digital circuits

A fast and memory-efficient diagnostic fault simulation for sequential circuits

Timing uncertainty analysis for time-of-flight systems

Provably correct high-level timing analysis without path sensitization

A timing analysis algorithm for circuits with level-sensitive latches

An object-oriented cell library manager

Reuse of design objects in CAD frameworks

Towards support for design description languages in EDA framework

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