NDLI: WCET analysis for multi-core processors with shared buses and event-driven bus arbitration

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WCET analysis for multi-core processors with shared buses and event-driven bus arbitration

Content Provider	ACM Digital Library
Author	Hack, Sebastian Hahn, Sebastian Jacobs, Michael
Abstract	Multi-core processors share common hardware resources between several processor cores. As a consequence, a program executed on one processor core may influence the execution time of the programs executed on the concurrent cores. This effect is commonly referred to as shared-resource interference. Worst-case execution time (WCET) analysis for multi-core processors has to take into account the shared-resource interference. Most existing approaches to WCET analysis for multi-core processors with shared buses and event-driven bus arbitration rely on compositionality. These approaches, however, do not support complex processor core pipelines. The existing approaches that support complex pipelines perform an exhaustive enumeration of possible interleavings of accesses to the shared bus by the different cores. Such an enumeration is infeasible in most cases. Our approach extends the state of the art in WCET analysis for single-core processors in such a way that it can deal with shared-bus interference. It does not rely on compositionality or enumeration of interleavings. Our approach calculates co-runner-insensitive WCET bounds, that are independent of the programs executed in parallel. Furthermore, it is able to improve those bounds by taking into account the bus access behavior of the concurrent cores and, thus, to calculate co-runner-sensitive WCET bounds. The implementation of our approach is evaluated for different multi-core processors. Our calculation of co-runner-insensitive WCET bounds is shown to be almost independent of the number of processor cores in terms of runtime and memory consumption. The co-runner-sensitive WCET bounds are up to 12.5% smaller than the co-runner-insensitive ones for a dual-core processor.
Starting Page	193
Ending Page	202
Page Count	10
File Format	PDF
ISBN	9781450335911
DOI	10.1145/2834848.2834872
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2015-11-04
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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