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| Content Provider | ACM Digital Library |
|---|---|
| Author | Hemachandra, L. Wallace, D. |
| Abstract | A probabilistic model is developed to study the process of automatic global wiring for LSI and VLSI chips. The probability parameter for this model is related to the local utilization rate and the channel supply on each global cell boundary. This theoretical relationship is compared with a real example, which agrees well with the theoretical prediction. Using Monte Carlo methods to obtain numerical solutions from the model, the effects of search region size on global routing probability are studied. There seems to be little gain in going more than one or two global cells beyond the minimum rectangle to find a path, regardless of the length of the connection. This conclusion is supported by the observation that the routing probability does not “scale” very accurately as the dimensions of the problem are increased. |
| Starting Page | 660 |
| Ending Page | 667 |
| Page Count | 8 |
| File Format | |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1981-06-29 |
| Access Restriction | Subscribed |
| Content Type | Text |
| Resource Type | Article |
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