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Content Provider | ACM Digital Library |
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Author | Heinrich, M. Hennessy, J. Heinlein, J. Gupta, A. Baxter, J. Chapin, J. Gharachorloo, K. Rosenblum, M. Simoni, R. Horowitz, M. Kuskin, J. Ofelt, D. Nakahira, D. |
Abstract | The FLASH multiprocessor efficiently integrates support for cache-coherent shared memory and high-performance message passing, while minimizing both hardware and software overhead. Each node in FLASH contains a microprocessor, a portion of the machine's global memory, a port to the interconnection network, an I/O interface, and a custom node controller called MAGIC. The MAGIC chip handles all communication both within the node and among nodes, using hardwired data paths for efficient data movement and a programmable processor optimized for executing protocol operations. The use of the protocol processor makes FLASH very flexible --- it can support a variety of different communication mechanisms --- and simplifies the design and implementation.This paper presents the architecture of FLASH and MAGIC, and discusses the base cache-coherence and message-passing protocols. Latency and occupancy numbers, which are derived from our system-level simulator and our Verilog code, are given for several common protocol operations. The paper also describes our software strategy and FLASH's current status. |
Starting Page | 302 |
Ending Page | 313 |
Page Count | 12 |
File Format | |
ISBN | 0818655100 |
DOI | 10.1145/191995.192056 |
Language | English |
Publisher | Association for Computing Machinery (ACM) |
Publisher Date | 1994-04-18 |
Access Restriction | Subscribed |
Content Type | Text |
Resource Type | Article |
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