NDLI: Probabilistic maximum error modeling for unreliable logic circuits

Please wait, while we are loading the content...

Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path

NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits

Simultaneous reduction in test data volume and test time for TRC-reseeding

Optimizing finfet technology for high-speed and low-power design

Exact sat-based toffoli network synthesis

Transition-activity aware design of reduction-stages for parallel multipliers

Side-channel resistant system-level design flow for public-key cryptography

A new decompression system for the configuration process of SRAM-based FPGAS

Design of mixed gates for leakage reduction

Synthesis of irregular combinational functions with large don't care sets

DFM issues for 65nm and beyond

Utilizing custom registers in application-specific instruction set processors for register spills elimination

A design methodology for space-time adapter

Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects

Effective heuristics for counterexample-guided abstraction refinement

An approximation algorithm for fully testable kEP-SOP networks

A new algorithm for the largest compositionally progressive solution of synchronous language equations

Efficient pipelining for modular multiplication architectures in prime fields

Floorplan repair using dynamic whitespace management

RT-level vector selection for realistic peak power simulation

Design challenges in 45nm and below: DFM, low-power and design for reliability

An optimized linear skewing interleave scheme for on-chip multi-access memory systems

Dummy fill aware buffer insertion during routing

SEU mitigation for sram-based fpgas through dynamic partial reconfiguration

Analysis of data dependence of leakage current in CMOS cryptographic hardware

Combinational equivalence checking for threshold logic circuits

Reducing snoop-energy in shared bus-based mpsocs by filtering useless broadcasts

Area efficient loop filter design for charge pump phase locked loop

Minimizing peak power in synchronous logic circuits

Modeling and estimating leakage current in series-parallel CMOS networks

DAG based library-free technology mapping

Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology

A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops

A 5 GHz wide band input and output matched low noise amplifier

Reducing verification overhead with RTL slicing

A coefficient optimization and architecture selection tool for SD modulators considering component non-idealities

An efficient cost-based canonical form for Boolean matching

Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor

Improved timing closure by early buffer planning in floor-placement design flow

A fast clock scheduling for peak power reduction in LSI

Sleep transistor distribution in row-based MTCMOS designs

I-cache multi-banking and vertical interleaving

Probabilistic gate-level power estimation using a novel waveform set method

Estimating path delay distribution considering coupling noise

Temperature-aware circuit design using adaptive body biasing

On-chip characterization of molecular electronic devices using CMOS: the design and simulation of a hybrid circuit based on experimental molecular electronic device results

GALS SoC interconnect bus for wireless sensor network processor platforms

A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS

Linearized CMOS active resistor independent on the bulk effect

Analyzing and modeling process balance for sub-threshold circuit design

Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint

Beyond 3G wireless communication system prototype

HW/SW partitioning using discrete particle swarm

A 900 MHz ISM band mash-12 fractional-n frequency synthesizer for 5-Mbps data transmission

Optimization techniques for BDD-based bisimulation computation

Hand-in-hand verification of high-level synthesis

Evaluation of using active circuitry for substrate noise suppression

Multi-segment $GF(2^{m})$ multiplication and its application to elliptic curve cryptography

An effective buffer planning algorithm for IP based fixed-outline SOC placement

A path based modeling approach for dynamic power estimation

Multi-processor operating system emulation framework with thermal feedback for systems-on-chip

A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for h.264/avc

Robust wiring networks for DfY considering timing constraints

Co-evolutionary high-level test synthesis

A buffered crossbar-based chip interconnection framework supporting quality of service

Operation limits in RTD-based ternary quantizers

Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors

A novel charge recycler for TFT-LCD source driver IC

Structured and tuned array generation (STAG) for high-performance random logic

Viewing direction-aware backlight scaling

An evolutionary approach for standard-cell library reduction

A new hardware architecture for performing the gridding of DNA microarray images

Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis

Design of an UHF RFID transponder for secure authentication

Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems

Area minimization algorithm for parallel prefix adders under bitwise delay constraints

The effect of temperature on cache size tuning for low energy embedded systems

New timing and routability driven placement algorithms for FPGA synthesis

Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor

Computer-aided design of 3d integrated circuits

Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC

Efficient space-time noc path allocation based on mutual exclusion and pre-reservation

Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers

Compiler assisted architectural exploration for coarse grained reconfigurable arrays

Skew spreading for peak current reduction

Future trends for wireless communication frontends in nanometer CMOS

Self-biased charge sampling amplifier in 90nm CMOS for medical ultrasound imaging

Block placement to ensure channel routability

RT level reliability enhancement by constructing dynamic TMRS

GA-SVM feasibility model and optimization kernel applied to analog IC design automation

An asynchronous fpga logic cell implementation

Physical aware clock skew rescheduling

Real-time implementation of a time-frequency analysis scheme

A low-power 333Mbps mobile-double data rate output driver with adaptive feedback to minimize overshoots and undershoots

Flexible blocks for high throughput serially concatenated convolutional codes

Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath

Novel architectures for efficient (m, n) parallel counters

Three-valued automated reasoning on analog properties

High CMRR current mode operational amplifier with a novel class AB input stage

On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors

Hardware architecture for matrix factorization in mimo receivers

Improvements for constraint solving in the systemc verification library

Reduced-complexity mimo detector with close-to ml error rate performance

Systematic design of two-stage operational amplifiers based on settling time and open-loop constraints

Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density

Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology

Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic

StateCharts to systemc: a high level hardware simulation approach

A symmetric mos current-mode logic universal gate for high speed applications

A lightweight parallel java execution environment for embedded multiprocessor systems-on-chip

An automated unique tagging system using CMOS process variation

Improvement of power distribution network using correlation-based regression analysis

A design kit for a fully working shared memory multiprocessor on FPGA

A high-level register optimization technique for minimizing leakage and dynamic power

Probabilistic maximum error modeling for unreliable logic circuits

An efficient net ordering algorithm for buffer insertion

Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

Address generation for nanowire decoders

Active bank switching for temperature control of the register file in a microprocessor

Probabilistic maximum error modeling for unreliable logic circuits

Content Provider	ACM Digital Library
Author	Lingasubramanian, Karthikeyan Bhanja, Sanjukta
Abstract	Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate failures due to the underlying device variabilities. Many of these failures would be transient in nature, necessitating the need for probabilistic logic base danalysis. Current research in this area is concerned with computing error bounds, but they do not account for circuits structures or are usually derived for specific logic gate types. In addition, the usual focus is on computing the average error behavior. In this work, we propose an exact probabilistic error model to compute the maximum error in a circuit-specific manner and can handle various types of logical components in the same circuit. We model the error estimation problem as a maximum a posteriori estimate (MAP) over the joint error probability function of the entire circuit. Using this model, we can not only compute the maximum error, but can also identify the input vector that cause the maximum output error. We demonstrate this model using MCNC and ISCAS circuits. We observe that for some circuits, maximum error probabilities are significantly larger than the average likelihood error, thus making acase for the consideration of maximum error metric as an essential design guideline rather than just average-case estimates. We also find that the error estimates depend on the specific circuit structure. Lastly, we observe that the maximum error probabilities are sensitive to the individual gate failure probabilities.
Starting Page	223
Ending Page	226
Page Count	4
File Format	PDF
ISBN	9781595936059
DOI	10.1145/1228784.1228842
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-03-11
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Maximum error Map
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in