NDLI: Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors

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Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors

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Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors

Content Provider	ACM Digital Library
Author	Tam, David Stumm, Michael Azimi, Reza
Abstract	The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end computing systems and game consoles have become shared memory multiprocessors with L1 and L2 cache sharing within a chip. Mid- and large-scale systems will have multiple processing chips and hence consist of an SMP-CMP-SMT configuration with non-uniform data sharing overheads. Current operating system schedulers are not aware of these new cache organizations, and as a result, distribute threads across processors in a way that causes many unnecessary, long-latency cross-chip cache accesses. In this paper we describe the design and implementation of a scheme to schedule threads based on sharing patterns detected online using features of standard performance monitoring units (PMUs) available in today's processing units. The primary advantage of using the PMU infrastructure is that it is fine-grained (down to the cache line) and has relatively low overhead. We have implemented our scheme in Linux running on an 8-way Power5 SMP-CMP-SMT multi-processor. For commercial multithreaded server workloads (VolanoMark, SPECjbb, and RUBiS), we are able to demonstrate reductions in cross-chip cache accesses of up to 70%. These reductions lead to application-reported performance improvements of up to 7%.
Starting Page	47
Ending Page	58
Page Count	12
File Format	PDF
ISBN	9781595936363
ISSN	01635980
DOI	10.1145/1272996.1273004
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-03-21
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Cache locality Performance monitoring unit Detecting sharing Cmp Resource allocation Thread migration Simultaneous multithreading Thread placement Thread scheduling Affinity scheduling Cache behavior Multithreading Hardware performance monitors Sharing Smp Shared caches Smt Single-chip multiprocessors Hardware performance counters
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Information Systems Hardware and Architecture

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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