NDLI: Specification Test Compaction for Analog Circuits and MEMS

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Technical Program Committee

Best Paper Awards

SoC in Nanoera: Challenges and Endless Possibility

Striking a New Balance in the Nanometer Era: First-Time-Right and Time-to-Market Demands Versus Technology Challenges

A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures

Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization

A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning

Reconfigurable Elliptic Curve Cryptosystems on a Chip

An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs

FPGA Architecture for Multi-Style Asynchronous Logic

Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?

On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips

Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture

The Challenges of Hardware Synthesis from C-Like Languages

Software Thread Integration and Synthesis for Real-Time Applications

Applying UML and MDA to Real Systems Design

Energy Bounds for Fault-Tolerant Nanoscale Designs

DVS for On-Chip Bus Designs Based on Timing Error Correction

Joint Power Management of Memory and Disk

Assertion-Based Design Exploration of DVS in Network Processor Architectures

Instruction Scheduling for Dynamic Hardware Configurations

A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware

Optimized Generation of Data-Path from C Codes for FPGAs

Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series

Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing

On Statistical Timing Analysis with Inter- and Intra-Die Variations

Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis

On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits

Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL

Noise Figure Evaluation Using Low Cost BIST

Specification Test Compaction for Analog Circuits and MEMS

Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach

IEEE 1149.4 Compatible ABMs for Basic RF Measurements

Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits

Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring

Energy-Aware Routing for E-Textile Applications

LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks

Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives

Lifetime Modeling of a Sensor Network

A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs

Activity Packing in FPGAs for Leakage Power Reduction

Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures

Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits

Leakage-Aware Interconnect for On-Chip Network

Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles

Symmetric Multiprocessing on Programmable Chips Made Easy

A Complete Network-On-Chip Emulation Framework

Low Cost Task Migration Initiation in a Heterogeneous MP-SoC

Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-Chip

Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit

MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption

Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance

Systematic Figure of Merit Computation for the Design of Pipeline ADC

Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters

Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices

Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits

Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques

Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown

An Accurate SER Estimation Method Based on Propagation Probability

Techniques for Fast Transient Fault Grading Based on Autonomous Emulation

TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques

Scheduling of Soft Real-Time Systems for Context-Aware Applications

Model Reuse through Hardware Design Patterns

A Public-Key Watermarking Technique for IP Designs

Design of a Virtual Component Neutral Network-on-Chip Transaction Layer

Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing

HEBS: Histogram Equalization for Backlight Scaling

Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach

A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors

Design Space Exploration for Dynamically Reconfigurable Architectures

A Dependability-Driven System-Level Design Approach for Embedded Systems

A Time Slice Based Scheduler Model for System Level Design

A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation

Automated Synthesis of Assertion Monitors using Visual Specifications

A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms

Statistical Timing Based Optimization using Gate Sizing

An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs

SAT-Based Complete Don't-Care Computation for Network Optimization

Efficient Solution of Language Equations Using Partitioned Representations

DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement

Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition

Uniformly-Switching Logic for Cryptographic Hardware

Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory

Memory Testing Under Different Stress Conditions: An Industrial Evaluation

Worst-Case and Average-Case Analysis of n-Detection Test Sets

Defect Aware Test Patterns

Computational Intelligence Characterization Method of Semiconductor Device

A New Embedded Measurement Structure for eDRAM Capacitor

Smart Temperature Sensor for Thermal Testing of Cell-Based ICs

An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor

Energy-Efficient, Utility Accrual Real-Time Scheduling Under the Unimodal Arbitrary Arrival Model

Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies

A New Task Model for Streaming Applications and Its Schedulability Analysis

Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling

Unified Modeling of Complex Real-Time Control Systems

Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique

Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions

Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints

Tag Overflow Buffering: An Energy-Efficient Cache Architecture

Q-DPM: An Efficient Model-Free Dynamic Power Management Technique

Hardware Accelerated Power Estimation

Integrated Electronics in the Car and the Design Chain Evolution or Revolution?

A New Approach to Component Testing

Process Oriented Software Quality Assurance - An Experience Report in Process Improvement - OEM Perspective

Embedded Automotive System Development Process

Functional Validation of System Level Static Scheduling

Defining an Enhanced RTL Semantics

RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC

Design for Verification of SystemC Transaction Level Models

Systematic Transaction Level Modeling of Embedded Systems with SystemC

Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures

Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark?

An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories

On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories

Increasing Register File Immunity to Transient Errors

An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories

Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software

Automatic Timing Model Generation by CFG Partitioning and Model Checking

A Contribution to Branch Prediction Modeling in WCET Analysis

Verifying Safety-Critical Timing and Memory-Usage Properties of Embedded Software by Abstract Interpretation

An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms

Design Method for Constant Power Consumption of Differential Logic Circuits

Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling

Low Power Oriented CMOS Circuit Optimization Protocol

Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction

Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip

Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage

Automotive System Architectures (Automotive Special Day)

Automotive System Design - Challenges and Potential

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