NDLI: Increasing FPGA resilience against soft errors using task duplication

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Silicon compilation: the answer to reducing IC development costs

The polygonal contraction heuristic for rectilinear Steiner tree construction

Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees

Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code

Embedded tutorial I: design for manufacturability

Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up

A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem

A formalism for functionality preserving system level transformations

Constraint extraction for pseudo-functional scan-based delay testing

Yield driven gate sizing for coupling-noise reduction under uncertainty

Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction

FSM re-engineering and its application in low power state encoding

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

Evaluation of the statistical delay quality model

Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?

On structure and suboptimality in placement

Low-power techniques for network security processors

Leakage power: trends, analysis and avoidance

Challenges to covering the high-level to silicon gap

TERPS: the embedded reliable processing system

Designing reliable circuit in the presence of soft errors

Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation

Floorplanning for 3-D VLSI design

MUP: a minimal unsatisfiability prover

Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise

Partial reluctance based circuit simulation is efficient and stable

Scalable interprocedural register allocation for high level synthesis

Low-power domino circuits using NMOS pull-up on off-critical paths

Automatic assume guarantee analysis for assertion-based formal verification

Are we ready for system-level synthesis?

Register placement for low power clock network

IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems

A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines

A 1GHz CMOS fourth-order continuous-time bandpass sigma delta modulator for RF receiver front end A/D conversion

Hardware/software partitioning for platform-based design method

A perturbation-aware noise convergence methodology for high frequency microprocessors

Customized on-chip memories for embedded chip multiprocessors

Three-dimensional place and route for FPGAs

A 2.4-GHz linear-tuning CMOS LC voltage-controlled oscillator

Instruction scheduling of VLIW architectures for balanced power consumption

Optimal module and voltage assignment for low-power

An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin

A function generator-based reconfigurable system

Panel III: EDA market in China

Modeling SystemC design in UML and automatic code generation

Supporting sequential assumptions in hybrid verification

An LP-based methodology for improved timing-driven placement

Evaluation of dual $V_{DD}$ fabrics for low power FPGAs

Design at the end of the silicon roadmap

An-OARSMan: obstacle-avoiding routing tree construction with good length performance

Time and energy efficient mapping of embedded applications onto NoCs

Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation

ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress

Analysis of buffered hybrid structured clock networks

Thermal-driven multilevel routing for 3-D ICs

Embedded software generation from system level specification for multi-tasking embedded systems

Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA

Maze routing with OPC consideration

Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams

Post-layout logic duplication for synthesis of domino circuits with complex gates

A processor core synthesis system in IP-based SoC design

Fault tolerant nanoelectronic processor architectures

Optimal placement by branch-and-price

A configurable AES processor for enhanced security

Opportunities and challenges for better than worst-case design

AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow

Effective analytical delay model for transistor sizing

Optimal redistribution of white space for wire length minimization

Integration of supercubing and learning in a SAT solver

Hierarchical analysis of process variation for mixed-signal systems

SAGA: synthesis technique for guaranteed throughput NoC architectures

Simultaneous floorplanning and resource binding: a probabilistic approach

Low-leakage robust SRAM cell design for sub-100nm technologies

TED+: a data structure for microprocessor verification

Skew scheduling and clock routing for improved tolerance to process variations

A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing

Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction

An elitist distributed particle swarm algorithm for RF IC optimization

Abstracting functionality for modular performance analysis of hard real-time systems

Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion

Performance driven reliable link design for networks on chips

Modern FPGA constrained placement

Adiabatic CMOS gate and adiabatic circuit design for low-power applications

Power minimization techniques on distributed real-time systems by global and local slack management

Bitwidth-aware scheduling and binding in high-level synthesis

Constructing zero-deficiency parallel prefix adder of minimum depth

Crossbar based design schemes for switch boxes and programmable interconnection networks

Enabling RTOS simulation modeling in a system level design language

Automatic functional test program generation for microprocessor verification

Placement stability metrics

Design of an application-specific PLD architecture

The development of integrated circuit industry in China

Making fast buffer insertion even faster via approximation techniques

Communication-driven task binding for multiprocessor with latency insensitive network-on-chip

Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs

A new method for model based frugal OPC

Clock network minimization methodology based on incremental placement

Wave-pipelined on-chip global interconnect

Scheduler implementation in MP SoC design

Propagation delay fault: a new fault model to test delay faults

Towards automatic parameter extraction for surface-potential-based MOSFET models with the genetic algorithm

A new approach for ring oscillator simulation using the harmonic balance method

Detecting support-reducing bound sets using two-cofactor symmetries

Speed and voltage selection for GALS systems based on voltage/frequency islands

An efficient control-oriented coverage metric

Detailed placement for improved depth of focus and CD control

Power estimation starategies for a low-power security processor

Microarchitecture evaluation with floorplanning and interconnect pipelining

Standard CMOS technology on-chip inductors with pn junctions substrate isolation

Achieving continuous $V_{T}$ performance in a dual $V_{T}$ process

Crowdedness-balanced multilevel partitioning for uniform resource utilization

Dynamic symmetry-breaking for improved Boolean optimization

A novel wavelet method for noise analysis of nonlinear circuits

Automated throughput-driven synthesis of bus-based communication architectures

Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions

Studying interactions between prefetching and cache line turnoff

Improved Boolean function hashing based on multiple-vertex dominators

Stability analysis of active clock deskewing systems using a control theoretic approach

An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

Exploiting temporal idleness to reduce leakage power in programmable architectures

Phase-locked loop synthesis using hierarchical divide-and-conquer multi-optimization

Optimizing intra-task voltage scheduling using data flow analysis

A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses

Dynamic power management using on demand paging for networked embedded systems

Clustering techniques for coarse-grained, antifuse FPGAs

An 11-bit 160-MS/s 1.35-V 10-mW D/A converter using automated device sizing system

A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors

Functionality directed clustering for low power MTCMOS design

An accurate 1.08-GHz CMOS LC voltage-controlled oscillator

A domain specific reconfigurable Viterbi fabric for system-on-chip applications

A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems

Forward symbolic model checking for real time systems

Redundant-via enhanced maze routing for yield improvement

Event-oriented computing with reconfigurable platform

Concurrent flip-flop and buffer insertion with adaptive blockage avoidance

System-level communication modeling for network-on-chip synthesis

SPIN-PAC: test compaction for speed-independent circuits

A multi-level transmission line network approach for multi-giga hertz clock distribution

Evaluation of on-chip transmission line interconnect using wire length distribution

Optimizing embedded applications using programmer-inserted hints

Oscillation ring based interconnect test scheme for SOC

Substrate resistance extraction with direct boundary element method

Efficient transient simulation for transistor-level analysis

Synthesis of quantum logic circuits

A system-level approach to hardware reconfigurable systems

An observability measure to enhance statement coverage metric for proper evaluation of verification completeness

Floorplan management: incremental placement for gate sizing and buffer insertion

Design and test of a scalable security processor

A bandwidth efficient subsampling-based block matching architecture for motion estimation

Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment

Partitioning and placement for buildable QCA circuits

A fast counterexample minimization approach with refutation analysis and incremental SAT

An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels

Simulation acceleration of transaction-level models for SoC with RTL sub-blocks

A fast algorithm for finding common multiple-vertex dominators in circuit graphs

The development of high performance FFT IP cores through hybrid low power algorithmic methodology

Lower bounds for dynamic BDD reordering

Process variation robust clock tree routing

A new register file access architecture for software pipelining in VLIW processors

Methodology for high level estimation of FPGA power consumption

A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18μm CMOS technology

FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection

VLSI on-chip power/ground network optimization considering decap leakage currents

An FPGA implementation of low-density parity-check code decoder with multi-rate capability

A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs

A class D audio power amplifier with high-efficiency and low-distortion

A dynamic voltage scaling algorithm for energy reduction in hard real-time systems

Wake-up protocols for controlling current surges in MTCMOS-based technology

Area-IO DRAM/logic integration with system-in-a-package (SiP)

Design of a high performance FFT processor based on FPGA

Multi-metric and multi-entity characterization of applications for early system design exploration

Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice

Interconnect estimation without packing via ACG floorplans

Reconfigurable adaptive FEC system with interleaving

Buffering global interconnects in structured ASIC design

MAIA: a framework for networks on chip generation and verification

A Huffman-based coding with efficient test application

Gibbs sampling in power grid analysis

Static analysis and automatic code synthesis of flexible FSM model

Bridging fault testability of BDD circuits

An efficient combinationality check technique for the synthesis of cyclic combinational circuits

Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits

STACCATO: disjoint support decompositions from BDDs through symbolic kernels

High-level synthesis for DSP applications using heterogeneous functional units

Tightly integrate dynamic verification with formal verification: a GSTE based approach

System-level design space exploration for security processor prototyping in analytical approaches

Design and measurement of 6.4 Gbps 8:1 multiplexer in 0.18μm CMOS process

PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits

Sequential equivalence checking using cuts

Statistical modeling of cross-coupling effects in VLSI interconnects

Battery-aware instruction generation for embedded processors

Partitioned model checking from software specifications

A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264

Leakage control in FPGA routing fabric

A dynamic reconfigurable RF circuit architecture

Compiler-directed selective data protection against soft errors

Probabilistic congestion model considering shielding for crosstalk reduction

Single-track asynchronous pipeline controller design

Resource sharing in pipelined CDFG synthesis

Substrate noise modeling in early floorplanning of MS-SOCs

An efficient dynamic task scheduling algorithm for battery powered DVS systems

On multiple-voltage high-level synthesis using algorithmic transformations

Design of an efficient memory subsystem for network processor

Increasing FPGA resilience against soft errors using task duplication

An integrated performance and power model for superscalar processor designs

Priority directed test generation for functional verification using neural networks

Timing driven track routing considering coupling capacitance

An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks

A wideband hierarchical circuit reduction for massively coupled interconnects

Library cell layout with Alt-PSM compliance and composability

Block based statistical timing analysis with extended canonical timing model

A design of high speed double precision floating point adder using macro modules

Compact and stable modeling of partial inductance and reluctance matrices

A variation-aware low-power coding methodology for tightly coupled buses

Automatic synthesis and scheduling of multirate DSP algorithms

Prediction of LC-VCOs' tuning curves with period calculation technique

Using data replication to reduce communication energy on chip multiprocessors

Design of clocked circuits using UML

Automatic extraction of function bodies from software binaries

Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platforms

Comparison of schemes for encoding unobservability in translation to SAT

Multilevel full-chip gridless routing considering optical proximity correction

Using GALS architecture to reduce the impact of long wire delay on FPGA performance

Forward discrete probability propagation method for device performance characterization under process variations

A low-power video segmentation LSI with boundary-active-only architecture

A flexible framework for communication evaluation in SoC design

Implication of assertion graphs in GSTE

Improving the scalability of SAMBA bus architecture

A novel configurable motion estimation architecture for high-efficiency MPEG-4/H.264 encoding

The design and implementation of a DVB receiving chip with PCI interface

Feasibility analysis of messages for on-chip networks using wormhole routing

XTW, a parallel and distributed logic simulator

Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling

A fast digit-serial systolic multiplier for finite field $GF(2^{m})$

Design and implementation of an SDH high-speed switch

A clustering technique to optimize hardware/software synchronization

Comprehensive frequency dependent interconnect extraction and evaluation methodology

Register-transfer level functional scan for hierarchical designs

Adaptive fuzzy control scheduling of window-constrained real-time systems

Design of vehicle position tracking system using short message services and its implementation on FPGA

Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration

On-chip thermal gradient analysis and temperature flattening for SoC design

Using fault model relaxation to diagnose real scan chain defects

A high performance QAM receiver for digital cable TV with integrated A/D and FEC decoder

Design of A 2.4-GHz integrated frequency synthesizer

On combining iteration space tiling with data space tiling for scratch-pad memory systems

Return path selection for loop RL extraction

A retention-aware test power model for embedded SRAM

Partitioned bus coding for energy reduction

An improved test access mechanism structure and optimization technique in system-on-chip

REMIC: design of a reactive embedded microprocessor core

Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects

On-chip accumulated jitter measurement for phase-locked loops

An improved bit-plane and pass dual parallel architecture for coefficient bit modeling in JPEG2000

Online hardware/software partitioning in networked embedded systems

Vector extraction for average total power estimation

SoC test scheduling using the B-tree based floorplanning technique

A generalized quadrature bandpass sampling in radio receivers

Comparing high-level modeling approaches for embedded system design

Relaxed hierarchical power/ground grid analysis

Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands

Reducing leakage power in instruction cache using WDC for embedded processors

Deriving a new efficient algorithm for min-period retiming

Sleep transistor sizing using timing criticality and temporal currents

Efficiently generating test vectors with state pruning

System-level architectural exploration using allocation-on-demand technique

K-disjointness paradigm with application to symmetry detection for incompletely specified functions

Timing analysis considering temporal supply voltage fluctuation

Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs

A fractional delay-locked loop for on chip clock generation applications

Logic optimization using rule-based randomized search

Fast, accurate MOS table model for circuit simulation using an unstructured grid and preserving monotonicity

Comprehensive analysis and optimization of CMOS LNA noise performance

A novel O(n) parallel banker's algorithm for System-on-a-Chip

Fast synthesis of exact minimal reversible circuits using group theory

Congestion prediction in floorplanning

An analog front-end IP for 13.56MHz RFID interrogators

Hardware/software co-design using hierarchical platform-based design method

Design and design automation of rectification logic for engineering change

CMP aware shuttle mask floorplanning

A two-stage genetic algorithm method for optimization the ΣΔ modulators

Architecture and performance comparison of a statistic-based lottery arbiter for shared bus on chip

Power minimization for dynamic PLAs

An improved P-admissible floorplan representation based on Corner Block List

A novel differential VCO circuit design for USB Hub

Using loop invariants to fight soft errors in data caches

Integrated algorithmic logical and physical design of integer multiplier

Fast floorplanning by look-ahead enabled recursive bipartitioning

Static power minimization in current-mode circuits

Arrival time aware scheduling to minimize clock cycle length

LFF algorithm for heterogeneous FPGA floorplanning

A novel transmitter for 1000Base-T physical transceiver

Efficient synthesis of speed-independent combinational logic circuits

Placement for configurable dataflow architecture

A novel data processing circuit in high-speed serial communication

A practical cut-based physical retiming algorithm for field programmable gate arrays

Wire congestion and thermal aware 3D global placement

A monolithic CMOS L band DAB receiver

BDD-based two variable sharing extraction

Placement with symmetry constraints for analog layout design using TCG-S

A bipolar IF amplifier/RSSI for ASK receiver

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