NDLI: Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms

Please wait, while we are loading the content...

CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors

Efficient aerial image simulation on multi-core SIMD CPU

On reconfiguration-oriented approximate adder design and its application

Model-based hardware design

Performance evaluation of multicore systems: from traffic analysis to latency predictions (embedded tutorial)

Improved SAT-based ATPG: more constraints, better compaction

Security-aware mapping for CAN-based real-time distributed automotive systems

Analog behavior in custom IC variation-aware design

Agent-based distributed power management for kilo-core processors

A high-performance triple patterning layout decomposer with balanced density

Computer-aided design of electrical energy systems

SDC-based modulo scheduling for pipeline synthesis

Dynamic thermal management in mobile devices considering the thermal coupling between battery and application processor

The overview of 2013 CAD contest at ICCAD

Compact lateral thermal resistance modeling and characterization for TSV and TSV array

Diagnosing root causes of system level performance violations

Improving platform energy: chip area trade-off in near-threshold computing environment

LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs

Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs

Scalable and efficient analog parametric fault identification

AMBER: adaptive energy management for on-chip hybrid video memories

Eagle-eye: a near-optimal statistical framework for noise sensor placement

Place and route for massively parallel hardware-accelerated functional verification

Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation space

MOMA: mapping of memory-intensive software-pipelined applications for systems with multiple memory controllers

Redundancy-aware electromigration checking for mesh power grids

Design with FinFETs: design rules, patterns, and variability

Spin torque devices in embedded memory: model studies and design space exploration

Why the design productivity gap never happened

Depth controlled symmetric function fanin tree restructure

FPGA simulation engine for customized construction of neural microcircuits

Optimization of interconnects between accelerators and shared memories in dark silicon

From statistical model checking to statistical model inference: characterizing the effect of process variations in analog circuits

Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees

Digital logic with molecular reactions

Sequential logic to transform probabilities

Generalized Boolean symmetries through nested partition refinement

Bayesian model fusion: a statistical framework for efficient pre-silicon validation and post-silicon tuning of complex analog and mixed-signal circuits

Hardware security: threat models and metrics

ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications

Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial time

ForTER: a forward error correction scheme for timing error resilience

BAG: a designer-oriented integrated framework for the development of AMS circuit generators

Automatic test pattern generation for delay defects using timed characteristic functions

Dynamic server power capping for enabling data center participation in power markets

A new methodology to address the growing productivity gap in analog design

Managing mobile platform power

Layout decomposition with pairwise coloring for multiple patterning lithography

A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring

Slack matching mode-based asynchronous circuits for average-case performance

Formal verification of distributed dynamic thermal management

ICCAD-2013 CAD contest in technology mapping for macro blocks and benchmark suite

On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs

Automatic concolic test generation with virtual prototypes for post-silicon validation

Leveraging rule-based designs for automatic power domain partitioning

Methodology for standard cell compliance and detailed placement for triple patterning lithography

Novel crack sensor for TSV-based 3D integrated circuits: design and deployment perspectives

An IDDQ-based source driver IC design-for-test technique

Thread-criticality aware dynamic cache reconfiguration in multi-core system

Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method

Techniques and challenges of implementing large scale logic design models in massively parallel fine-grained multiprocessor systems

Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization

An efficient compiler framework for cache bypassing on GPUs

Scalable power grid transient analysis via MOR-assisted time-domain simulations

Exploring Boolean and non-Boolean computing with spin torque devices

In-placement clock-tree aware multi-bit flip-flop generation for power optimization

Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing

A polynomial time algorithm for solving the word-length optimization problem

Hardware implementation of BLTL property checkers for acceleration of statistical model checking

Low-power timing closure methodology for ultra-low voltage designs

Noise in genetic circuits: hindrance or chance?

Automated generation of efficient instruction decoders for instruction set simulators

Encoding multi-valued functions for symmetry

Uncertainty quantification for integrated circuits: stochastic spectral methods

A proof-carrying based framework for trusted microprocessor IP

Design of cross-point metal-oxide ReRAM emphasizing reliability and cost

Efficient analog layout prototyping by layout reuse with routing preservation

Aging-aware logic synthesis

DREAMS: DFM rule EvAluation using manufactured silicon

An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems

Constrained pattern assignment for standard cell based triple patterning lithography

Considering fabrication in sustainable computing

Sensitization criterion for threshold logic circuits and its application

STEAM: a fast compact thermal model for two-phase cooling of integrated circuits

ICCAD-2013 CAD contest in placement finishing and benchmark suite

The impact of shallow trench isolation effects on circuit performance

Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms

Performance boosting under reliability and power constraints

POLAR: placement based on novel rough legalization and refinement

Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs

Hardware Trojans in wireless cryptographic ICs: silicon demonstration & detection method evaluation

A disturb-alleviation scheme for 3D flash memory

High-performance gate sizing with a signoff timer

An efficient graph sparsification approach to scalable harmonic balance (HB) analysis of strongly nonlinear RF circuits

A just-in-time customizable processor

A vectorless framework for power grid electromigration checking

Clock power minimization using structured latch templates and decision tree induction

Optimization of polymerase chain reaction on a cyberphysical digital microfluidic biochip

DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems

Proof logging for computer algebra based SMT solving

Incremental multiple-scan chain ordering for ECO flip-flop insertion

Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os

Approximate logic synthesis under general error magnitude and frequency constraints

Simulation of temporal stochastic phenomena in electronic and biological systems: a comparative review, examples and synergies

A write-time based memristive PUF for hardware security applications

Stochastic error rate estimation for adaptive speed control with field delay testing

PROTON: an automatic place-and-route tool for optical networks-on-chip

Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library

FPGA acceleration of enhanced boolean constraint propagation for SAT solvers

ICCAD-2013 CAD contest in mask optimization and benchmark suite

Unleashing the potential of MLC STT-RAM caches

Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis

Modeling and analysis of (nonstationary) low frequency noise in nano devices: a synergistic approach based on stochastic chemical kinetics

Temperature tracking: an innovative run-time approach for hardware Trojan detection

Parallel power grid analysis using preconditioned GMRES solver on CPU-GPU platforms

Trace alignment algorithms for offline workload analysis of heterogeneous architectures

Conquering the scheduling alternative explosion problem of SystemC symbolic simulation

Post-route alleviation of dense meander segments in high-performance printed circuit boards

ISOMER: integrated selection, partitioning, and placement methodology for reconfigurable architectures

Partial synthesis through sampling with and without specification

Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms

Content Provider	ACM Digital Library
Author	Lee, Doowon Nahir, Amir Mammo, Biruk Gal, Raviv Bertacco, Valeria Chatterjee, Debapriya Morad, Ronny Ziv, Avi
Abstract	Software-based simulation provides a convenient environment for microprocessor design validation, where a number of complex software checkers are integrated with the simulated design to identify discrepancies between design and specification. Unfortunately, the performance of software-based simulation is vastly inadequate to achieve sufficient coverage for large microprocessor designs with complex microarchitectures. Hence, acceleration and emulation platforms are heavily deployed in the industry for high-performance validation. However, software checkers cannot be directly incorporated into such platforms, forcing designers to craft ad-hoc solutions. Adapting checking solutions for software simulation to acceleration platforms presents the following constraints: i) only a limited number of signals can be monitored per cycle for checking purposes so as to retain acceptable simulation performance, and ii) the overhead of the added checking logic must be minimal. In this work, we explore a novel solution to adapt software-based checkers for individual microarchitectural blocks to acceleration platforms, by leveraging a hybrid approach. Our solution exploits embedded logic and data tracing for post-simulation checking in a synergistic fashion to limit the associated overhead. Embedded logic can be used for synthesized local checkers as well as to compress the traced data and thus limit recording overhead. We analyze several trade-offs associated with checking accuracy and logic/recording overhead for different microarchitectural blocks of an out-of-order superscalar processor design. We strive to provide valuable insights on how to adapt such software checkers to the acceleration environment using our hybrid approach. We find that, by leveraging simple embedded checkers and data compressors (15-25% logic overhead), we can achieve excellent checking accuracy even when aggressively compressing the data for transfer (only 15-25 bits/cycle), and localize bugs up to 5,900 cycles sooner than an architectural-level checker.
Starting Page	311
Ending Page	317
Page Count	7
File Format	PDF
ISBN	9781479910694
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2013-11-18
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in