NDLI: Ubiquitous memory introspection

Please wait, while we are loading the content...

Message from the General Chairs

Message from the Program Chairs

Organizing Committee

Reviewers

Corporate Sponsors

GPU Computing: Programming a Massively Parallel Processor

Parallel Programming Environment: A Key to Translating Tera-Scale Platforms into a Big Success

Understanding Tradeoffs in Software Transactional Memory

Code Generation and Optimization for Transactional Memory Constructs in an Unmanaged Language

Run-Time Support for Optimizations Based on Escape Analysis

Evaluating Indirect Branch Handling Mechanisms in Software Dynamic Translation Systems

Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications

Virtual Cluster Scheduling Through the Scheduling Graph

On the Complexity of Register Coalescing

A Dimension Abstraction Approach to Vectorization in Matlab

Microarchitecture Sensitive Empirical Models for Compiler Optimizations

Iterative Optimization in the Polyhedral Model: Part I, One-Dimensional Time

Evaluating Heuristic Optimization Phase Order Search Algorithms

Loop Optimization using Hierarchical Compilation and Kernel Decomposition

Rapidly Selecting Good Compiler Optimizations using Performance Counters

Shadow Profiling: Hiding Instrumentation Costs with Parallelism

SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance

Compilation Techniques for Real-Time Java Programs

Compiler-Directed Variable Latency Aware SPM Management to CopeWith Timing Problems

Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection

Graph-Based Procedural Abstraction

Structure Layout Optimization for Multithreaded Programs

Code Compaction of an Operating System Kernel

Ubiquitous memory introspection

Pipelined Execution of Critical Sections Using Software-Controlled Caching in Network Processors

Isla Vista Heap Sizing: Using Feedback to Avoid Paging

Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping

Heterogeneous Clustered VLIW Microarchitectures

Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors

Author Index

Ubiquitous memory introspection

Content Provider	ACM Digital Library
Author	Rudolph, Larry Wong, Weng-Fai Zhao, Qin Amarasinghe, Saman Rabbah, Rodric
Abstract	Modern memory systems play a critical role in the performance of applications, but a detailed understanding of the application behavior in the memory system is not trivial to attain. It requires time consuming simulations and detailed modeling of the memory hierarchy, often using long address traces. It is increasingly possible to access hardware performance counters to count relevant events in the memory system, but the measurements are coarse-grained and better suited for performance summaries than providing instruction level feedback. The availability of a low cost, online, and accurate methodology for deriving finegrained memory behavior profiles can prove extremely useful for runtime analysis and optimization of programs. This paper presents a new methodology for Ubiquitous Memory Introspection (UMI). It is an online and lightweight methodology that uses fast mini-simulations to analyze short memory access traces recorded from frequently executed code regions. The simulations provide profiling results at varying granularities, down to that of a single instruction or address. UMI naturally complements runtime optimizations and enables new opportunities for online memory specific optimizations. We present a prototype runtime system implementing UMI. The prototype has an average runtime overhead of 14%. This overhead is only 1% more than a state of the art binary instrumentation tool. We used 32 benchmarks, including the full suite of SPEC CPU2000 benchmarks, for evaluation. We show that the mini-simulations accurately reflect the cache performance of two existing memory systems, an Intel Pentium 4 and an AMD Athlon MP (K7). We also demonstrate that UMI predicts delinquent load instructions with an 88% rate of accuracy for applications with a relatively high number of cache misses, and 61% overall. The online profiling results are used at runtime to implement a simple software prefetching strategy that achieves an overall speedup of 64% in the best case.
Starting Page	299
Ending Page	311
Page Count	13
File Format	PDF
ISBN	0769527647
DOI	10.1109/CGO.2007.12
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2007-03-11
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Introspection-based memory de-duplication and migration

Ubiquitous Memory Introspection (Preliminary Manuscript) (2006)

Tappan Zee (north) bridge: mining memory accesses for introspection

Enforcing authorization policies using transactional memory introspection

SPECTRE: A dependable introspection framework via System Management Mode

An implementation and semantics for transactional memory introspection in Haskell

Forenscope: a framework for live forensics

IBMon: monitoring VMM-bypass capable InfiniBand devices using memory introspection

Semantics-Driven Introspection in a Virtual Environment

Ubiquitous memory introspection

Similar Documents

Introspection-based memory de-duplication and migration

Ubiquitous Memory Introspection (Preliminary Manuscript) (2006)

Tappan Zee (north) bridge: mining memory accesses for introspection

Enforcing authorization policies using transactional memory introspection

SPECTRE: A dependable introspection framework via System Management Mode

An implementation and semantics for transactional memory introspection in Haskell

Forenscope: a framework for live forensics

IBMon: monitoring VMM-bypass capable InfiniBand devices using memory introspection

Semantics-Driven Introspection in a Virtual Environment

Ubiquitous memory introspection