NDLI: Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard

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Qualifying Precision of Abstract SystemC Models Using the SystemC Verification Standard

Content Provider	ACM Digital Library
Author	Ip, C. Norris Carbognani, Franco Lennard, Christopher K. Cochrane, Allan Bates, Paul
Abstract	The increasing complexity of Systems on Chip (SoC) has introduced the need for abstract executable specifications (models) covering both hardware and embedded software. The new capabilities of SystemC 2.0, such as those added for transaction-based communication and test-bench Specification and monitoring, facilitate this SoC modeling. However, an obstacle to the adoption of abstract modeling as standard design practice is the lack of well establishes methodologies for the assessment of model precision. We describe such a methodology based on the SystemC Verification Standard implemented by Cadence's TestBuilder-SC. This methodology enables comparison of high-level (transaction level) SoC models in SystemC against implementation RTL models. An application of the methodology is presented, based on the AMBA Class Library (ACL) for SystemC being developed by ARM in collaboration with EDA partners. The key elements of the methodology are: 1. A completely reusable testbench that can be used for simulation and verification of the design at both high-level (transaction level) of abstraction and RTL implementation level. 2. A single database format is used so that data collected from simulations at each level can easily be processed and compared We present an example of effective validation of ARM PrimeXsys-platform IP components against their RTL implementation.
File Format	PDF
ISBN	0769518702
ISSN	15301591
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-03-03
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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