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| Content Provider | ACM Digital Library |
|---|---|
| Author | Strum, M. Chau, Wang Jiang Lopes de Oliveira, D. Chiepa Cunha, W. |
| Abstract | This article proposes a methodology to synthesize extended burst asynchronous state machines operating in a new mode which we called input burst/output burst (I/sub b//O/sub b/), while obeying the bounded gate and wire delay model. In such machines a new input burst is accepted as soon as the last output signal is activated. Such an operation is faster than the machines operating in the fundamental mode because the latter must achieve a stable state before accepting a new input burst. We present a set of conditions that guarantee critical race and hazard free operation of the resulting circuits. Our synthesis methodology starts from the well known extended burst mode specification. A new state minimization algorithm is performed to obtain the minimum number of states that are required to solve the state transition conflicts. A set of state and output equations are derived for a sum-of-product implementation. A D flip flop design is shown in order to illustrate the methodology. A theoretical analysis is presented to show the speed increase of our circuits with respect to the equivalent machines obtained by the 3D and the UCLOCK methodologies (which start from the same specification). |
| ISBN | 076950843X |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 2000-09-18 |
| Access Restriction | Subscribed |
| Subject Keyword | Critical race and hazard free operation Extended burst mode D flip flop design Hazards and race conditions Asynchronous state machines Wire delay model Finite state machines Asynchronous circuits Flip-flops State minimization algorithm State transition conflicts Uclock methodologies Input burst/output burst Sum-of-product implementation Bounded gate model Delays High level synthesis Output equations |
| Content Type | Text |
| Resource Type | Article |
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