NDLI: On the Interaction Between Power-Aware FPGA CAD Algorithms

Please wait, while we are loading the content...

Conference Committee

Technical Program Committee

Tutorial 2: Leakage Issues in IC Design: Trends, Estimation, and Avoidance

Tutorial 1: LINUX for EDA

Tutorial 3: Recent Advances in Formal Verification

Tutorial 4: Embedded Software Development

Sunday Panel: CAD for High-End Design: Help, Hope, or Hype?

Monday Panel: Semiconductor Slowdown: Who Will Blink First?

Adapative Error Protection for Energy Efficiency

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips

The Y-Architecture for On-Chip Interconnect: Analysis and Methodology

Generalized Network Flow Techniques for Dynamic Voltage Scaling in Hard Real-Time Systems

Approaching the Maximum Energy Saving on Embedded Systems with Multiple Voltages

Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems

RTL Power Optimization with Gate-Level Accuracy

Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications

Achieving Design Closure Through Delay Relaxation Parameter

Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading

Bus-Driven Floorplanning

A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning

Placement Method Targeting Predictability Robustness and Performance

Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach

Partial Core Encryption for Performance-Efficient Test of SOCs

TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers

Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints

Moment-Based Power Estimation in Very Deep Submicron Technologies

IDAP: A Tool for High Level Power Estimation of Custom Array Structures

SOI Transistor Model for Fast Transient Simulation

Design and CAD Challenges in sub-90nm CMOS Technologies

Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation

A Framework for Constrained Functional Verification

Generator-based Verification

Efficient Generation of Monitor Circuits for GSTE Assertion Graphs

Weibull Based Analytical Waveform Model

Equivalent Waveform Propagation for Static Timing Analysis

Timing Analysis in Presence of Power Supply and Ground Voltage Variations

Vectorless Analysis of Supply Noise Induced Delay Variation

Array Composition and Decomposition for Optimizing Embedded Applications

Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design

Energy Optimization of Distributed Embedded Processors by Combined Data Compression and Functional Partitioning

Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems

Retiming for Wire Pipelining in System-On-Chip

Retiming with Interconnect and Gate Delay

Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels

Clock Scheduling and Clocktree Construction for High Performance ASICS

Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification

A Generalized Method for Computing Oscillator Phase Noise Spectra

Efficient Iterative Time Preconditioners for Harmonic Balance RF Circuit Simulation

Fredkin/Toffoli Templates for Reversible Logic Synthesis

Evaluation of Placement Techniques for DNA Probe Array Layout

Physical And Reduced-Order Dynamic Analysis of MEMS

Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs

A Scalable Application-Specific Processor Synthesis Methodology

INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors

An Enhanced Multilevel Algorithm for Circuit Placement

Fractional Cut: Improved Recursive Bisection Placement

On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis

SATORI - A Fast Sequential SAT Engine for Circuits

CAMA: A Multi-Valued Satisfiability Solver

The Compositional Far Side of Image Computation

Cache Optimization For Embedded Processor Cores: An Analytical Approach

Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems

Performance Efficiency of Context-Flow System-on-Chip Platform

Amplification of Ultrawideband Signals

A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs

Systematic Design for Power Minimization of Pipelined Analog-to-Digital Converters

A Framework for Designing Reusable Analog Circuits

A Fast Crosstalk- and Performance-Driven Multilevel Routing System

A Min-Cost Flow Based Detailed Router for FPGAs

Length-Matching Routing for High-Speed Printed Circuit Boards

Analytical Bound for Unwanted Clock Skew due to Wire Width Variation

Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement

Iterative Abstraction using SAT-based BMC with Proof Analysis

Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits

System Level Design and Verification Using a Synchronous Language

Noise Analysis for Optical Fiber Communication Systems

Analog Macromodeling using Kernel Methods

A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits

Incremental Placement for Timing Optimization

A Trade-off Oriented Placement Tool

Optimality and Stability Study of Timing-Driven Placement Algorithms

A Probabilistic-Based Design Methodology for Nanoscale Computation

Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation

Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics

A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits

A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers

Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization

LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches

Compiler-Based Register Name Adjustment for Low-Power Embedded Processors

Gradual Relaxation Techniques with Applications to Behavioral Synthesis

Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication

Binding, Allocation and Floorplanning in Low Power High-Level Synthesis

A High-level Interconnect Power Model for Design Space Exploration

A Probabilistic Approach to Buffer Insertion

Simultaneous Analytic Area and Power Optimization for Repeater Insertion

Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion

Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing

Dynamic Data-bit Memory Built-In Self- Repair

FAME: A Fault-Pattern Based Memory Failure Analysis Framework

Hardware/Software Co-testing of Embedded Memories in Complex SOCs

Block-based Static Timing Analysis with Uncertainty

"AU: Timing Analysis Under Uncertainty

Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal

Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches

Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone Systems

Dynamic Platform Management for Configurable Platform-Based System-on-Chips

A General S-Domain Hierarchical Network Reduction Algorithm

Branch Merge Reduction of RLCM Networks

A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC Lines

Mixed Signal DFT: A Concise Overview

Manufacturing-Aware Physical Design

A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits

Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level

On the Interaction Between Power-Aware FPGA CAD Algorithms

A Theory of Non-Deterministic Networks

Stable Multiway Circuit Partitioning for ECO

Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization

An Algorithmic Approach for Generic Parallel Adders

FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits

Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis

Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage

Static Verification of Test Vectors for IR Drop Failure

ATPG for Noise-Induced Switch Failures in Domino Logic

Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations

A Methodology for the Computation of an Upper Bound on Nose Current Spectrum of CMOS Switching Activity

SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation

SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects

Multi-Domain Clock Skew Scheduling

Clock Period Minimization of Non-Zero Clock Skew Circuits

Minimum-Area Sequential Budgeting for FPGA

ILP Models for the Synthesis of Asynchronous Control Circuits

Passive Synthesis of Compact Frequency-Dependent Interconnect Models via Quadrature Spectral Rules

Analytic Modeling of Interconnects for Deep Sub-Micron Circuits

A New Surface Integral Formulation For Wideband Impedance Extraction of 3-D Structures

Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis

On Compacting Test Response Data Containing Unknown Values

Adjustable Width Linear Combinational Scan Vector Decompression

On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic

Formal Methods for Dynamic Power Management

Large-Scale Circuit Placement: Gap and Promise

Multi-Million Gate FPGA Physical Design Challenges

Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations

A Statistical Gate-Delay Model Considering Intra-Gate Variability

Statistical Clock Skew Analysis Considering Intra-Die Process Variations

On the Interaction Between Power-Aware FPGA CAD Algorithms

Content Provider	ACM Digital Library
Author	Lamoureux, Julien Wilton, Steven J. E.
Abstract	As Field-Programmable Gate Array (FPGA) power consumptioncontinues to increase, lower power FPGA circuitry, architectures,and Computer-Aided Design (CAD) tools need to be developed.Before designing low-power FPGA circuitry, architectures, orCAD tools, we must first determine where the biggest savings (interms of energy dissipation) are to be made and whether thesesavings are cumulative. In this paper, we focus on FPGA CADtools. Specifically, we describe a new power-aware CAD flow forFPGAs that was developed to answer the above questions.Estimating energy using very detailed post-route power and delaymodels, we determine the energy savings obtained by our power-awaretechnology mapping, clustering, placement, and routingalgorithms and investigate how the savings behave when thealgorithms are applied concurrently. The individual savings of thepower-aware technology-mapping, clustering, placement, androuting algorithms were 7.6%, 12.6%, 3.0%, and 2.6%respectively. The majority of the overall savings were achievedduring the technology mapping and clustering stages of the power-awareFPGA CAD flow. In addition, the savings were mostlycumulative when the individual power-aware CAD algorithmswere applied concurrently with an overall energy reduction of 22.6%.
File Format	PDF
ISBN	1581137621
ISSN	10923152
DOI	10.1109/ICCAD.2003.106
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2003-11-09
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Software Computer Science Applications

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in