NDLI: Combined partitioning and data padding for scheduling multiple loop nests

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Combined partitioning and data padding for scheduling multiple loop nests

Content Provider	ACM Digital Library
Author	Wang, Zhong Sha, Edwin H.-M. Hu, Xiaobo Sharon
Abstract	With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective way to exploit the data locality. Traditional loop partition techniques, however, consider only a singleton nested loop. This paper presents multiple loop partition scheduling technique, which combines the loop partition and data padding to generate the detailed partition schedule. The computation and data prefetching are balanced in the partition schedule, such that the long memory latency can be hidden efficiently. Multiple loop partition scheduling explores parallelism among computations, and exploit the data locality between different loop nests as well in each loop nest. Data padding is applied in our technique to eliminate the cache interference, which overcomes the problem of cache conflict misses arisen from loop partition. Therefore, our technique can be applied in architectures with low associativity cache. The experiments show that multiple loop partition scheduling can achieve the significant improvement over the existing methods.
Starting Page	67
Ending Page	75
Page Count	9
File Format	PDF
ISBN	1581133995
DOI	10.1145/502217.502228
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2001-11-16
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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