NDLI: A unified approach to constrained mapping and routing on network-on-chip architectures

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A unified approach to constrained mapping and routing on network-on-chip architectures

Content Provider	ACM Digital Library
Author	Hansson, Andreas Rǎdulescu, Andrei Goossens, Kees
Abstract	One of the key steps in Network-on-Chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called Unified MApping, Routing and Slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder System-on-Chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach.
Starting Page	75
Ending Page	80
Page Count	6
File Format	PDF
ISBN	1595931619
DOI	10.1145/1084834.1084857
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2005-09-19
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Network-on-chip Routing Mapping Quality-of-service System-on-chip
Content Type	Text
Resource Type	Article

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