NDLI: Device optimization for ultra-low power digital sub-threshold operation

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Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation

Improved clock-gating through transparent pipelining

Impact of technology scaling on energy aware execution cache-based microarchitectures

Delay optimal low-power circuit clustering for FPGAs with dual supply voltages

Characterizing and modeling minimum energy operation for subthreshold circuits

HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction

Post-layout leakage power minimization based on distributed sleep transistor insertion

Maximizing efficiency of solar-powered systems by load matching

Approaches to run-time and standby mode leakage reduction in global buses

Microarchitectural power modeling techniques for deep sub-micron microprocessors

On optimality of adiabatic switching in MOS energy-recovery circuit

A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach

Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbps

The design of a low power asynchronous multiplier

Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization

Reducing radio energy consumption of key management protocols for wireless sensor networks

Efficient adaptive voltage scaling system through on-chip critical path emulation

Why hot chips are no longer "cool"

Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS

Microarchitectural techniques for power gating of execution units

$Single-v_{DD}$ and $single-v_{T}$ super-drowsy techniques for low-leakage high-performance instruction caches

Creating a power-aware structured ASIC

Device optimization for ultra-low power digital sub-threshold operation

Location cache: a low-power L2 cache system

Total power optimization through simultaneously $multiple-v_{DD}$ $multiple-v_{TH}$ assignment and device sizing with stack forcing

Power utility maximization for multiple-supply systems by a load-matching switch

Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses

Power-optimal pipelining in deep submicron technology

Constant-load energy recovery memory for efficient high-speed operation

Integrated adaptive DC/DC conversion with adaptive pulse-train technique for low-ripple fast-response regulation

Low-power asynchronous viterbi decoder for wireless applications

Low-power fixed-width array multipliers

On optimality of adiabatic switching in MOS energy-recovery circuit

Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systems

An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes

Balanced energy optimization

Technology exploration for adaptive power and frequency scaling in 90nm CMOS

SEPAS: a highly accurate energy-efficient branch predictor

Design and implementation of correlating caches

Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems

Nanoscale CMOS circuit leakage power reduction by double-gate device

A way-halting cache for low-energy high-performance systems

Active mode leakage reduction using fine-grained forward body biasing strategy

Dynamic voltage and frequency scaling based on workload decomposition

A new algorithm for improved VDD assignment in low power dual VDD systems

Application-level prediction of battery dissipation

A comparative study of MOS VCOs for low voltage high performance operation

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation

A CMOS even harmonic mixer with current reuse for low power applications

Low-power carry-select adder using adaptive supply voltage based on input vector patterns

Energy-aware demand paging on NAND flash-based embedded storages

Experience with a low power wireless mobile computing platform

Memory-aware energy-optimal frequency assignment for dynamic supply voltage scaling

Battery life challenges on future mobile notebook platforms

Experimental measurement of a novel power gating structure with intermediate power saving mode

Understanding the energy efficiency of simultaneous multithreading

Dynamic power management for streaming data

ESACW: an adaptive algorithm for transmission power reduction in wireless networks

4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors

Soft error and energy consumption interactions: a data cache perspective

A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations

Architecting voltage islands in core-based system-on-a-chip designs

Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces

Minimizing power consumption and complexity in a programmable transmit filter bank for OFDM

A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies

2.45 GHz power and data transmission for a low-power autonomous sensors platform

A novel continuous-time common-mode feedback for low-voltage switched-OPAMP

Reducing pipeline energy demands with local DVS and dynamic retiming

Application adaptive energy efficient clustered architectures

FSM--based power modeling of wireless protocols: the case of bluetooth

Preemption-aware dynamic voltage scaling in hard real-time systems

Managing standby and active mode leakage power in deep sub-micron design

Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses

Any-time probabilistic switching model using bayesian networks

Understanding nanoscale conductors

The impact of variability on power

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