NDLI: Toward formalizing a validation methodology using simulation coverage

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General Chair's Welcome

Executive Committee

Technical Program Committee

1997 Best Paper Award

ACSEE Undergraduate Scholarships

Design Automation Conference Graduate Scholarship Awards

SIGDA Meritorious Service Award

35th Call for Papers

Opening Keynote Address-Scott G. McNealy

Thursday Keynote Address-Michael A. Aymar

An executive view of the EDA industry (panel)

An improved algorithm for minimum-area retiming

Efficient latch optimization using exclusive sets

Sequence compaction for probabilistic analysis of finite-state machines

Synthesis of speed-independent circuits from STG-unfolding segment

Telescopic units: increasing the average throughput of pipelined designs by adaptive latency control

Zeros and passivity of Arnoldi-reduced-order models for interconnect networks

Preservation of passivity during RLC network reduction via split congruence transformations

Lumped interconnect models via Gaussian quadrature

Calculating worst-case gate delays due to dominant capacitance coupling

Schedule validation for embedded reactive real-time systems

Incorporating imprecise computation into system-level design of application-specific heterogeneous multiprocessors

Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets

An efficient implementation of reactivity for modeling hardware in the scenic design environment

Tools and methodologies for low power design

Low-power design tools—where is the impact? (panel)

A C-based RTL design verification methodology for complex microprocessor

Hierarchical random simulation approach for the verification of S/390 CMOS multiprocessors

Efficient testing of clock regenerator circuits in scan designs

A real-time RTL engineering-change method supporting on-line debugging for logic-emulation applications

A graph-based synthesis algorithm for AND/XOR networks

Optimizing designs containing black boxes

Solving covering problems using LPR-based lower bounds

Exact coloring of real-life graphs is easy

Hierarchical 2-D field solution for capacitance extraction for VLSI interconnect modeling

Bounds for BEM capacitance extraction

SPIE: sparse partial inductance extraction

A fast method of moments solver for efficient parameter extraction of MCMs

Static timing analysis of embedded software

A task-level hierarchical memory model for system synthesis of multiprocessors

Predicting timing behavior in architectural design exploration of real-time embedded systems

Formal verification of a superscalar execution unit

Formal verification of content addressable memories using symbolic trajectory evaluation

Formal verification of FIRE: a case study

Interface-based design

An integrated design environment for performance and dependability analysis

A dynamic design estimation and exploration environment

Remembrance of things past: locality and memory in BDDs

Linear sifting of decision diagrams

Safe BDD minimization using don't cares

Timing optimization for multi-source nets: characterization and optimal repeater insertion

Exact required time analysis via false path detection

Symbolic timing verification of timing diagrams using Presburger formulas

Code generation for core processors

Physical design and synthesis (panel): merge or die!

Interface timing verification drives system design

Memory-CPU size optimization for embedded system designs

Methodology for behavioral synthesis-based algorithm-level design space exploration: DCT case study

Formal verification in a commercial setting

Equivalence checking using cuts and heaps

Efficient methods for simulating highly nonlinear multi-rate circuits

Rapid frequency-domain analog fault simulation under parameter tolerances

SWITTEST: automatic switch-level fault simulation and test evaluation of switched-capacitor systems

Analysis and evaluation of address arithmetic capabilities in custom DSP architectures

System level fixed-point design based on an interpolative approach

ISDL: an instruction set description language for retargetability

Generation of software tools from processor descriptions for hardware/software codesign

Education for the deep submicron age: business as usual?

InfoPad—an experiment in system level design and integration

Very rapid prototyping of wearable computers: a case study of custom versus off-the-shelf design methodologies

CAD at the design-manufacturing interface

CELLERITY: a fully automatic layout synthesis system for standard cell libraries

Developing a concurrent methodology for standard-cell library generation

A fast and accurate technique to optimize characterization tables for logic synthesis

Limited exception modeling and its use in presynthesis optimizations

Potential-driven statistical ordering of transformations

Synthesis of application specific programmable processors

Symbolic evaluation of performance models for tradeoff visualization

Power macromodeling for high level power estimation

Statistical estimation of the cumulative distribution function for power dissipation in VLSI cirucits

Statistical estimation of average power dissipation in sequential circuits

Vector generation for maximum instantaneous current through supply lines for CMOS circuits

Fast hardware/software co-simulation for virtual prototyping and trade-off analysis

Dynamic communication models in embedded system co-simulation

Challenges in worldwide IP reuse (panel with embedded tutorial): applying VSIA standards to system on chip design

Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks

Transistor sizing issues and tool for multi-threshold CMOS technology

Architectural exploration using Verilog-based power estimation: a case study of the IDCT

A power estimation framework for designing low power portable video applications

An investigation of power delay trade-offs on PowerPC circuits

Power management techniques for control-flow intensive designs

Low energy memory and register allocation using network flow

Power-conscious high level synthesis using loop folding

The future of custom cell generation in physical synthesis

CLIP: an optimizing layout generator for two-dimensional CMOS cells

An efficient transistor folding algorithm for row-based CMOS layout design

Technology retargeting for IC layout

A test synthesis approach to reducing BALLAST DFT overhead

STARBIST: scan autocorrelated random pattern generation

A hybrid algorithm for test point selection for scan-based BIST

Hardware/software co-verification (panel)

Design and synthesis of array structured telecommunication processing applications

RASSP virtual prototyping of DSP systems

A parallel/serial trade-off methodology for look-up table based decoders

High-level power modeling, estimation, and optimization

A network flow approach for hierarchical tree partitioning

Multi-way FPGA partitioning by fully exploiting design hierarchy

A hierarchy-driven FPGA partitioning method

Multilevel hypergraph partitioning: application in VLSI domain

Multilevel circuit partitioning

Hierarchical test generation and design for testability of ASPPs and ASIPs

Frequency-domain compatibility in digital filter BIST

A scheme for integrated controller-datapath fault testing

The next-generation HDL (panel)

Executable workflows: a paradigm for collaborative design on the Internet

Electronic component information exchange (ECIX)

Modeling design tasks and tools: the link between product and flow model

Hierarchical sequence compaction for power estimation

Profile-driven program synthesis for evaluation of system power dissipation

Analytical estimation of transition activity from word-level signal statistics

Wire segmenting for improved buffer insertion

More practical bounded-skew clock routing

An efficient approach to multi-layer layer assignment with application to via minimization

Optimal wire-sizing function with fringing capacitance consideration

Fault simulation under the multiple observation time approach using backward implications

ATPG for heat dissipation minimization during scan testing

Automatic generation of synchronous test patterns for asynchronous circuits

The road ahead in CPLD & FPGA design methodology (panel)

Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology

Accurate and efficient macromodel of submicron digital standard cells

Power supply noise analysis methodology for deep-submicron VLSI chip design

FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits

Technology-dependent transformations for low-power synthesis

Low power FPGA design—a re-engineering approach

Post-layout logic restructuring for performance optimization

Layout driven re-synthesis for low power consumption LSIs

Overview of microelectromechanical systems and design processes

CAD and foundries for microsystems

Structured design of microelectromechanical systems

Algorithms for coupled domain MEMS simulation

A hardware/software partitioner using a dynamically determined granularity

System-level synthesis of low-power hard real-time systems

COSYN: hardware-software co-synthesis of embedded systems

Data-flow assisted behavioral partitioning for embedded systems

Hardware/software partitioning and pipelining

Chip parasitic extraction and signal integrity verification (extended abstract)

Nosie and signal integrity in deep submicron design (panel)

Designing high performance CMOS microprocessors using full custom techniques

Disjunctive partitioning and partial iterative squaring: an effective approach for symbolic traversal of large circuits

An efficient assertion checker for combinational properties

Toward formalizing a validation methodology using simulation coverage

Algorithms for large-scale flat placement

Quadratic placement revisited

Unification of budgeting and placement

Cluster refinement for block placement

The EDA startup experience (panel): financing the venture

Computer-aided design of free-space opto-electronic systems

Hardware/software co-simulation in a VHDL-based test bench approach

Am embedded system case study: the firm ware development environment for a multimedia audio processor

Toward formalizing a validation methodology using simulation coverage

Content Provider	ACM Digital Library
Author	Ashar, Pranav Gupta, Aarti Malik, Sharad
Abstract	The biggest obstacle in the formal verification of large designs istheir very large state spaces, which cannot be handled even bytechniques such as implicit state space traversal. The only viablesolution in most cases is validation by functional simulation. Unfortunately, this has the drawbacksof high computationalrequirementsdue to the large number of test vectors needed, and the lack of adequate coverage measures to characterize the quality of a given testset. To overcome these limitations, there has been recent interest inhybrid techniques which combine the strengths of formal verification and simulation. Formal verification-based techniques are usedon a test model (usually much smaller than the design) to derive a setof functional test vectors, which are then used for design validationthrough simulation. The test set generated typically satisfies somecoverage measure on the test model. Recent research has proposedthe use of state or transition coverage. However, no effort has beenmade to relate these measures to the coverage of design errors. Furthermore, the derivation of the test model remains largely ad-hoc,with few formal guidelines.We demonstrate that under a given set of assumptions, transitiontours on test models can be used for complete validation of an implementation against a specification, for a large and important classof designs that includes many programmable/hardwired, general-purpose processors/DSPs. A by-product of this study is specificguidelines for deriving the test model, motivated by the requirement of providing complete coverage of all errors. We illustrate theapplication of our methodology on a pipelined implementation of the DLX processor.
Starting Page	740
Ending Page	745
Page Count	6
File Format	PDF
ISBN	0897919203
DOI	10.1145/266021.266359
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1997-06-13
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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