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  1. Proceedings of the Workshop on Programmable Routers for Extensible Services of Tomorrow (PRESTO '10)
  2. Controlling parallelism in a multicore software router
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Distributed runtime load-balancing for software routers on homogeneous many-core processors
Use cases and deployment of Juniper's high-end programmable routers
Frenetic: a high-level language for OpenFlow networks
A policy-based constraint-solving platform towards extensible wireless channel selection and routing
Controlling parallelism in a multicore software router
Recent progress in the GENI project
Evaluating the suitability of server network cards for software routers
Introducing standby capabilities into next-generation network devices
Forwarding path architectures for multicore software routers
Virtualizing the network forwarding plane
Leveraging router programmability for traffic matrix computation
Adaptive multi-task monitoring system based on overhead prediction

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Controlling parallelism in a multicore software router

Content Provider ACM Digital Library
Author Iannaccone, Gianluca Argyraki, Katerina Manesh, Maziar Dobrescu, Mihai Ratnasamy, Sylvia
Abstract Software routers promise to enable the fast deployment of new, sophisticated kinds of packet processing without the need to buy and deploy expensive new equipment. The challenge is offering such programmability while at the same time achieving a competitive level of performance. Recent work has demonstrated that software routers are capable of high performance, but only for conventional, simple workloads (like packet forwarding and IP routing) and, even that, after careful manual calibration. In contrast, we are interested in achieving high performance in the context of a software router running multiple sophisticated packet-processing applications. In particular: first, we identify the main factors that affect packet-processing performance on a modern multicore general-purpose server---cache misses, cache contention, load-balancing across processing cores; then, we formulate an optimization problem that takes as input a particular server architecture and a packet processing flow, and determines how to parallelize the router's functionality across the available cores so as to maximize its throughput.
Starting Page 1
Ending Page 6
Page Count 6
File Format PDF
ISBN 9781450304672
DOI 10.1145/1921151.1921154
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2010-11-30
Publisher Place New York
Access Restriction Subscribed
Content Type Text
Resource Type Article
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