NDLI: Measurement based WCET Analysis for Multi-core Architectures

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Measurement based WCET Analysis for Multi-core Architectures

Content Provider	ACM Digital Library
Author	Knoll, Alois Coombes, Andrew Shah, Hardik Huang, Kai Raabe, Andreas
Abstract	The interference on shared resources caused by concurrently executing applications unpredictably prolongs their execution. Hence, determination of the Worst Case Execution Time (Wcet) of applications executing on shared memory multi-core processors is hard to estimate. This hinders the adoption of Commercial Off The Shelf (Cots) multi-core processors in hard real-time systems. The existing techniques opt for tailored multi-core architectures to provide high computation power at predictable execution time. However, this approach yields poor resource utilization and high costs. In this paper, we present a technique to measure the Wcet of applications on multi-core architectures using existing measurement based timing analysis tools. Our technique has a minor area impact (≈ 5%). However, this impact is limited to the emulation devices only and production chips remain unchanged. Thus, our technique does not impact performance of the Cots chips by any ways. The technique is demonstrated by measuring Wcet of benchmark applications using the RapiTime timing analysis tool. The tests are conducted on a quad-core NIOS II processor on an Altera Fpga.
Starting Page	257
Ending Page	266
Page Count	10
File Format	PDF
ISBN	9781450327275
DOI	10.1145/2659787.2659819
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-10-08
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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