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Instruction decomposition and microprogramming by exception in a generalized processor
| Content Provider | ACM Digital Library |
|---|---|
| Author | Dillion, Jerry |
| Abstract | A control structure is described whereby a limited set of tagged commands achieves the function of the typical fetch, decode, and execute processes of a higher level instruction but with fewer steps and decreased execution time than that required by the usual microprogramming. It is based on the decomposition of an instruction rather than the implementation of the fetch-decode-execute cycle. This results in a higher-level instruction set in which the lower level tagged commands are a primitive subset in contrast to typical emulation in which the two levels are incompatible. A firmware routine is only necessary for the more complex or seldom used instructions, hence the term microprogramming by exception. This approach offers the low cost, flexibility, and potential for extensive instruction sets of microprogramming without their serious execution time, control memory and implementation effort penalties. The set of tagged commands in a computer now under development is given, and examples of the implementation of higher-level instructions are provided. |
| Starting Page | 33 |
| Ending Page | 40 |
| Page Count | 8 |
| DOI | 10.1145/800150.808833 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1974-01-01 |
| Publisher Place | New York |
| Access Restriction | Subscribed |
| Content Type | Text |
| Resource Type | Article |
