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| Content Provider | ACM Digital Library |
|---|---|
| Author | Dickson, Ross M. Plakal, Manoj Moore, Kevin E. Sorin, Daniel J. Martin, Milo M. K. Ailamaki, Anatassia Wood, David A. Alameldeen, Alaa R. Mauer, Carl J. Hill, Mark D. |
| Abstract | Symmetric muultiprocessor (SMP) servers provide superior performance for the commercial workloads that dominate the Internet. Our simulation results show that over one-third of cache misses by these applications result in cache-to-cache transfers, where the data is found in another processor's cache rather than in memory. SMPs are optimized for this case by using snooping protocols that broadcast address transactions to all processors. Conversely, directory-based shared-memory systems must indirectly locate the owner and sharers through a directory, resulting in larger average miss latencies.This paper proposes timestamp snooping, a technique that allows SMPs to i) utilize high-speed switched interconnection networks and ii) exploit physical locality by delivering address transactions to processors and memories without regard to order. Traditional snooping requires physical ordering of transactions. Timestamp snooping works by processing address transactions in a logical order. Logical time is maintained by adding a few bits per address transaction and having network switches perform a handshake to ensure on-time delivery. Processors and memories then reorder transactions based on their timestamps to establish a total order.We evaluate timestamp snooping with commercial workloads on a 16-processor SPARC system using the Simics full-system simulator. We simulate both an indirect (butterfly) and a direct (torus) network design. For OLTP, DSS, web serving, web searching, and one scientific application, timestamp snooping with the butterfly network runs 6-28% faster than directories, at a cost of 13-43% more link traffic. Similarly, with the torus network, timestamp snooping runs 6-29% faster for 17-37% more link traffic. Thus, timestamp snooping is worth considering when buying more interconnect bandwidth is easier than reducing interconnect latency. |
| Starting Page | 25 |
| Ending Page | 36 |
| Page Count | 12 |
| File Format | |
| ISSN | 01635980 |
| DOI | 10.1145/384264.378998 |
| Journal | ACM SIGOPS Operating Systems Review (OPSR) |
| Volume Number | 34 |
| Issue Number | 5 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1975-04-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Networks and Communications Hardware and Architecture Information Systems |
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