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| Content Provider | ACM Digital Library |
|---|---|
| Author | Odersky, Martin Rompf, Tiark Lee, HyoukJoong Jonnalagedda, Manohar Jovanovic, Vojin Sujeeth, Arvind K. Amin, Nada Brown, Kevin J. Olukotun, Kunle |
| Abstract | High level data structures are a cornerstone of modern programming and at the same time stand in the way of compiler optimizations. In order to reason about user- or library-defined data structures compilers need to be extensible. Common mechanisms to extend compilers fall into two categories. Frontend macros, staging or partial evaluation systems can be used to programmatically remove abstraction and specialize programs before they enter the compiler. Alternatively, some compilers allow extending the internal workings by adding new transformation passes at different points in the compile chain or adding new intermediate representation (IR) types. None of these mechanisms alone is sufficient to handle the challenges posed by high level data structures. This paper shows a novel way to combine them to yield benefits that are greater than the sum of the parts. Instead of using staging merely as a front end, we implement internal compiler passes using staging as well. These internal passes delegate back to program execution to construct the transformed IR. Staging is known to simplify program generation, and in the same way it can simplify program transformation. Defining a transformation as a staged IR interpreter is simpler than implementing a low-level IR to IR transformer. With custom IR nodes, many optimizations that are expressed as rewritings from IR nodes to staged program fragments can be combined into a single pass, mitigating phase ordering problems. Speculative rewriting can preserve optimistic assumptions around loops. We demonstrate several powerful program optimizations using this architecture that are particularly geared towards data structures: a novel loop fusion and deforestation algorithm, array of struct to struct of array conversion, object flattening and code generation for heterogeneous parallel devices. We validate our approach using several non trivial case studies that exhibit order of magnitude speedups in experiments. |
| Starting Page | 497 |
| Ending Page | 510 |
| Page Count | 14 |
| File Format | PDF MP4 |
| ISSN | 03621340 15581160 |
| DOI | 10.1145/2480359.2429128 |
| Journal | ACM SIGPLAN Notices (SIGP) |
| Volume Number | 48 |
| Issue Number | 1 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1983-05-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Code generation Extensible compilers Staging Data structures |
| Content Type | Audio Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Software |
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