NDLI: Post-compilation optimization for multiple gains with pattern matching

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Post-compilation optimization for multiple gains with pattern matching

Content Provider	ACM Digital Library
Author	Gupta, Amit Pankaj, B. S. Ghosh, Mrinmoy Kumar, Rajeev Chakrabarti, P. P.
Abstract	Many existing retargetable compilers for ASIPs and domain-specific processors generate low quality code since the compiler is not able to fully utilize the intricacies of ISA of these processors. Hence, there is a need to further optimize the code produced by these compilers. In this paper, we introduce a new post-compilation optimization technique which is based on finding repeating instruction patterns in generated code and replacing them with their optimized equivalents. The instruction patterns to be found are represented by finite state machines which allow encapsulation of multiple patterns in just one representation, and instructions in a pattern to be not necessarily lexically adjacent. We also present a conflict resolution algorithm to select an optimization whenever a set of instructions fall under two or more different patterns of which only one can be applied on the basis of code size, cycle count or switching activity improvement. We tested this technique on the compiled binaries of ARM and Intel processors for code size improvement. We discuss the possible applications of this strategy in design space exploration (DSE) of embedded processors.
Starting Page	14
Ending Page	23
Page Count	10
File Format	PDF
ISSN	03621340 15581160
DOI	10.1145/1117303.1117306
Journal	ACM SIGPLAN Notices (SIGP)
Volume Number	40
Issue Number	12
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1983-05-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Peephole optimization Instruction set fsm Post-compilation optimization Pattern matching
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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