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| Content Provider | ACM Digital Library |
|---|---|
| Author | Koskinen, Eric Cook, Byron |
| Abstract | Branching-time temporal logics (e.g. CTL, CTL*, modal mu-calculus) allow us to ask sophisticated questions about the nondeterminism that appears in systems. Applications of this type of reasoning include planning, games, security analysis, disproving, precondition synthesis, environment synthesis, etc. Unfortunately, existing automatic branching-time verification tools have limitations that have traditionally restricted their applicability (e.g. push-down systems only, universal path quantifiers only, etc). In this paper we introduce an automation strategy that lifts many of these previous restrictions. Our method works reliably for properties with non-trivial mixtures of universal and existential modal operators. Furthermore, our approach is designed to support (possibly infinite-state) programs. The basis of our approach is the observation that existential reasoning can be reduced to universal reasoning if the system's state-space is appropriately restricted. This restriction on the state-space must meet a constraint derived from recent work on proving non-termination. The observation leads to a new route for implementation based on existing tools. To demonstrate the practical viability of our approach, we report on the results applying our preliminary implementation to a set of benchmarks drawn from the Windows operating system, the PostgreSQL database server, SoftUpdates patching system, as well as other hand-crafted examples. |
| Starting Page | 219 |
| Ending Page | 230 |
| Page Count | 12 |
| File Format | |
| ISSN | 03621340 15581160 |
| DOI | 10.1145/2499370.2491969 |
| Journal | ACM SIGPLAN Notices (SIGP) |
| Volume Number | 48 |
| Issue Number | 6 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1983-05-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Model checking Ctl Termination Program analysis Temporal logic Formal verification |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Software |
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