NDLI: Complexity analysis and algorithm design for reorganizing data to minimize non-coalesced memory accesses on GPU

Content Provider	ACM Digital Library
Author	Zhao, Zhijia Zhang, Eddy Zheng Wu, Bo Jiang, Yunlian Shen, Xipeng
Abstract	The performance of Graphic Processing Units (GPU) is sensitive to irregular memory references. Some recent work shows the promise of data reorganization for eliminating non-coalesced memory accesses that are caused by irregular references. However, all previous studies have employed simple, heuristic methods to determine the new data layouts to create. As a result, they either do not provide any performance guarantee or are effective to only some limited scenarios. This paper contributes a fundamental study to the problem. It systematically analyzes the inherent complexity of the problem in various settings, and for the first time, proves that the problem is NP-complete. It then points out the limitations of existing techniques and reveals that in practice, the essence for designing an appropriate data reorganization algorithm can be reduced to a tradeoff among space, time, and complexity. Based on that insight, it develops two new data reorganization algorithms to overcome the limitations of previous methods. Experiments show that an assembly composed of the new algorithms and a previous algorithm can circumvent the inherent complexity in finding optimal data layouts, making it feasible to minimize non-coalesced memory accesses for a variety of irregular applications and settings that are beyond the reach of existing techniques.
Starting Page	57
Ending Page	68
Page Count	12
File Format	PDF
ISSN	03621340 15581160
DOI	10.1145/2517327.2442523
Journal	ACM SIGPLAN Notices (SIGP)
Volume Number	48
Issue Number	8
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1983-05-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Memory coalescing Data transformation Thread-data remapping Computational complexity Gpgpu Runtime optimizations
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Complexity analysis and algorithm design for reorganizing data to minimize non-coalesced memory accesses on GPU

Complexity analysis and algorithm design for reorganizing data to minimize non-coalesced memory accesses on gpu ∗.

On-the-fly elimination of dynamic irregularities for GPU computing (SIGP, Vol. 46, Issue. 3)

On-the-fly elimination of dynamic irregularities for GPU computing

Streamlining GPU applications on the fly: thread divergence elimination through runtime thread-data remapping

On-the-fly elimination of dynamic irregularities for GPU computing (CARN, Vol. 39, Issue. 1)

A study towards optimal data layout for GPU computing

JolokiaC++: Optimizing Irregular Accesses for GPGPU

Optimizing remote accesses for offloaded kernels:application to high-level synthesis for FPGA

Complexity analysis and algorithm design for reorganizing data to minimize non-coalesced memory accesses on GPU

Similar Documents

Complexity analysis and algorithm design for reorganizing data to minimize non-coalesced memory accesses on GPU

Complexity analysis and algorithm design for reorganizing data to minimize non-coalesced memory accesses on gpu ∗.

On-the-fly elimination of dynamic irregularities for GPU computing (SIGP, Vol. 46, Issue. 3)

On-the-fly elimination of dynamic irregularities for GPU computing

Streamlining GPU applications on the fly: thread divergence elimination through runtime thread-data remapping

On-the-fly elimination of dynamic irregularities for GPU computing (CARN, Vol. 39, Issue. 1)

A study towards optimal data layout for GPU computing

JolokiaC++: Optimizing Irregular Accesses for GPGPU

Optimizing remote accesses for offloaded kernels:application to high-level synthesis for FPGA

Complexity analysis and algorithm design for reorganizing data to minimize non-coalesced memory accesses on GPU