NDLI: Automatic instruction scheduler retargeting by reverse-engineering

Content Provider	ACM Digital Library
Author	Ottoni, Guilherme Bridges, Matthew J. Vachharajani, Neil August, David I.
Abstract	In order to generate high-quality code for modern processors, a compiler must aggressively schedule instructions, maximizing resource utilization for execution efficiency. For a compiler to produce such code, it must avoid structural hazards by being aware of the processor's available resources and of how these resources are utilized by each instruction. Unfortunately, the most prevalent approach to constructing such a scheduler, manually discovering and specifying this information, is both tedious and error-prone. This paper presents a new approach which, when given a processor or processor model, automatically determines this information. After establishing that the problem of perfectly determining a processor's structural hazards through probing is not solvable, this paper proposes a heuristic algorithm that discovers most of this information in practice. This can be used either to alleviate the problems associated with manual creation or to verify an existing specification. Scheduling with these automatically derived structural hazards yields almost all of the performance gain achieved using perfect hazard information.
Starting Page	228
Ending Page	238
Page Count	11
File Format	PDF
ISSN	03621340 15581160
DOI	10.1145/1133255.1134008
Journal	ACM SIGPLAN Notices (SIGP)
Volume Number	41
Issue Number	6
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1983-05-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Instruction scheduling Automatic retargeting Structural hazard Reverse-engineering Compilers
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Software

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