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| Content Provider | ACM Digital Library |
|---|---|
| Author | Gray, Kathryn E. Deacon, Will Sarkar, Susmit Flur, Shaked Sezgin, Ali Pulte, Christopher Sewell, Peter Maranget, Luc |
| Abstract | In this paper we develop semantics for key aspects of the ARMv8 multiprocessor architecture: the concurrency model and much of the 64-bit application-level instruction set (ISA). Our goal is to clarify what the range of architecturally allowable behaviour is, and thereby to support future work on formal verification, analysis, and testing of concurrent ARM software and hardware. Establishing such models with high confidence is intrinsically difficult: it involves capturing the vendor's architectural intent, aspects of which (especially for concurrency) have not previously been precisely defined. We therefore first develop a concurrency model with a microarchitectural flavour, abstracting from many hardware implementation concerns but still close to hardware-designer intuition. This means it can be discussed in detail with ARM architects. We then develop a more abstract model, better suited for use as an architectural specification, which we prove sound w.r.t.~the first. The instruction semantics involves further difficulties, handling the mass of detail and the subtle intensional information required to interface to the concurrency model. We have a novel ISA description language, with a lightweight dependent type system, letting us do both with a rather direct representation of the ARM reference manual instruction descriptions. We build a tool from the combined semantics that lets one explore, either interactively or exhaustively, the full range of architecturally allowed behaviour, for litmus tests and (small) ELF executables. We prove correctness of some optimisations needed for tool performance. We validate the models by discussion with ARM staff, and by comparison against ARM hardware behaviour, for ISA single- instruction tests and concurrent litmus tests. |
| Starting Page | 608 |
| Ending Page | 621 |
| Page Count | 14 |
| File Format | |
| ISSN | 03621340 15581160 |
| DOI | 10.1145/2914770.2837615 |
| Journal | ACM SIGPLAN Notices (SIGP) |
| Volume Number | 51 |
| Issue Number | 1 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1983-05-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Semantics Isa Relaxed memory models |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Software |
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