NDLI: A framework for architecture-level power, area, and thermal simulation and its application to network-on-chip design exploration

Content Provider	ACM Digital Library
Author	Hsieh, Ming-yu Thompson, Kevin Song, William Rodrigues, Arun Riesen, Rolf
Abstract	We describe the integrated power, area and thermal modeling framework in the Structural Simulation Toolkit (SST) for large-scale high performance computer simulation. It integrates various power and thermal modeling tools and computes run-time energy dissipation for core, network on chip, memory controller and shared cache. It also has functionality to update the leakage power as temperature changes. We illustrate the utilization of the framework by applying it to explore interconnect options in manycore systems with consideration of temperature variation and leakage feedback. We compare power, energy-delay-area product (EDAP), and energy-delay product (EDP) of four manycore configurations-1 core, 2 cores, 4 cores and 8 cores per cluster. Results from simulation with or without consideration of temperature variation both show that the 4-core per cluster configuration has the best EDAP and EDP. Even so, considering temperature variation increases total power dissipation. We demonstrate the importance of considering temperature variation in the design ow. With this power, area and thermal modeling capability, SST can be used for hardware/software co-design of future Exascale systems.
Starting Page	63
Ending Page	68
Page Count	6
File Format	PDF
ISSN	01635999
DOI	10.1145/1964218.1964229
Journal	ACM SIGMETRICS Performance Evaluation Review (PERV)
Volume Number	38
Issue Number	4
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-01-10
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Noc Power consumption Performance modeling Simulation framework
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Hardware and Architecture Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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