NDLI: Design algorithms for asynchronous operations in cache memory

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Design algorithms for asynchronous operations in cache memory

Content Provider	ACM Digital Library
Author	Hać, Anna
Abstract	The algorithms used to operate on disk buffer cache memory have significant impact on operating system performance. The buffer cache size, the size of the file being written, the disk access time, and the algorithms used to append updated blocks from the buffer cache to the disk queue determine performance of operations in disk cache memory. The determination of these algorithms is particularly important since they are implemented in the system kernel and cannot be changed by the user or system administrator.This paper introduces new algorithms for asynchronous operations in disk buffer cache memory. These algorithms allow for writing the files into the buffer cache by the processes. The number of active processes in the system and the length of the queue to the disk buffer cache are considered in the algorithm design. This information is obtained dynamically during the execution of the algorithms. The performance of the operations on the buffer cache is improved by using the algorithms, which allow for writing the contents of the buffer cache to the disk depending on the system load and the write activity. The elapsed time of writing a file into the buffer cache is calculated. The waiting time to start writing a file is also considered. It is shown that the elapsed time of writing a file decreases by using the algorithms, which write the blocks to the disk depending on the rate of write operations and the number of active processes in the system. The time for a block to become available for update in the buffer cache is given. The number of blocks available for update in the buffer cache is derived. The performance of the algorithms is compared. It is shown that the proposed algorithms allow for better performance than an algorithm that does not use the information about the system load.
Starting Page	21
Ending Page	21
Page Count	1
File Format	PDF
ISSN	01635999
DOI	10.1145/1041911.1041914
Journal	ACM SIGMETRICS Performance Evaluation Review (PERV)
Volume Number	16
Issue Number	2-4
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-01-10
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Hardware and Architecture Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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