NDLI: On reordering instruction streams for pipelined computers

Content Provider	ACM Digital Library
Author	Shieh, J. J. Papachristou, C.
Abstract	This paper describes a method to reorder the straight line instruction streams for pipelined computers which have one instruction issue unit but may contain multiple function units. The objective is to make the most efficient usage of the pipelines within the computer system. The input to the scheduler is the intermediate code of a compiler, and is represented by a data dependence graph (DDG).The scheduler is a kind of list scheduler. The data dependence and the pipeline effect of the function units within the system have been considered for finding a most suitable time slot for each node during reordering time.The scheduler has been implemented and several scientific application programs have been tested. The results show that in most of the cases the scheduler will achieve the optimal result. The average instruction issue rate is over 96%. As a comparison, the issue rate of an ordinary compiler is only 22%; and the issue rate of a compiler with the effect of pipeline but without reordering the instruction stream is about 45%.
Starting Page	199
Ending Page	206
Page Count	8
File Format	PDF
ISSN	1050916X
DOI	10.1145/75395.75419
Journal	ACM SIGMICRO Newsletter (SIGM)
Volume Number	20
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1978-03-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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On reordering instruction streams for pipelined computers