NDLI: A study of scalar compilation techniques for pipelined supercomputers (CARN, Vol. 15, Issue. 5)

Content Provider	ACM Digital Library
Author	Weiss, Shlomo Smith, James E.
Abstract	This paper studies two compilation techniques for enhancing scalar performance in high-speed scientific processors: software pipelining and loop unrolling. We study the impact of the architecture (size of the register file) and of the hardware (size of instruction buffer) on the efficiency of loop unrolling. We also develop a methodology for classifying software pipelining techniques. For loop unrolling, a straightforward scheduling algorithm is shown to produce near-optimal results when not inhibited by recurrences or memory hazards. Software pipelining requires less hardware but also achieves less speedup. Finally, we show that the performance produced with a modified CRAY-1S scalar architecture and a code scheduler utilizing loop unrolling is comparable to the performance achieved by the CRAY-1S with a vector unit and the CFT vectorizing compiler.
Starting Page	105
Ending Page	109
Page Count	5
File Format	PDF
ISSN	01635964
DOI	10.1145/36177.36191
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	15
Issue Number	5
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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A study of scalar compilation techniques for pipelined supercomputers (CARN, Vol. 15, Issue. 5)