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| Content Provider | ACM Digital Library |
|---|---|
| Author | Sauer, Wolfram Hilgendorf, Rolf |
| Abstract | The IBM™ S/390™ architecture is a complex architecture, which has grown over a long period of time. Typical implementations use microcode to cope with the more complex instructions and facilities of S/390. Current IBM S/390 processors even contain two levels of microcode.We report on an experimental S/390 processor based on a RISC processor kernel employing superscalar, out of order execution of instructions. S/390 instructions have to be translated into internal sequences of RISC instructions. Actually two closely coupled internal sequences - one for register based execution and one for storage based execution are generated. The translation is a straight-forward mapping in most cases with some flexibility for special instructions.The paper introduces the hardware mechanisms used for mapping S/390 instructions to internal sequences. The facilities, which provide a greater degree of flexibility are discussed. The interactions of the low-level mapping scheme with the microcode levels is examined. Finally we discuss our experiences with this type of implementation of a CISC architecture on a RISC processor kernel. |
| Starting Page | 37 |
| Ending Page | 42 |
| Page Count | 6 |
| File Format | |
| ISSN | 01635964 |
| DOI | 10.1145/373574.373588 |
| Journal | ACM SIGARCH Computer Architecture News (CARN) |
| Volume Number | 29 |
| Issue Number | 1 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1981-04-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Content Type | Text |
| Resource Type | Article |
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