NDLI: Optimized on-chip pipelining of memory-intensive computations on the cell BE (CARN, Vol. 36, Issue. 5)

Content Provider	ACM Digital Library
Author	Keller, Jörg Kessler, Christoph W.
Abstract	Multiprocessors-on-chip, such as the Cell BE processor, regularly suffer from restricted bandwidth to off-chip main memory. We propose to reduce memory bandwidth requirements, and thus increase performance, by expressing our application as a task graph, by running dependent tasks concurrently and by pipelining results directly from task to task where possible, instead of buffering in off-chip memory. To maximize bandwidth savings and balance load simultaneously, we solve a mapping problem of tasks to SPEs on the Cell BE. We present three approaches: an integer linear programming formulation that allows to compute Paretooptimal mappings for smaller task graphs, general heuristics, and a problem speci c approximation algorithm. We validate the mappings for dataparallel computations and sorting.
Starting Page	36
Ending Page	45
Page Count	10
File Format	PDF
ISSN	01635964
DOI	10.1145/1556444.1556450
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	36
Issue Number	5
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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Optimized on-chip pipelining of memory-intensive computations on the cell BE (CARN, Vol. 36, Issue. 5)