NDLI: Code layout optimizations for transaction processing workloads

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Volume 29, Issue 5, December 2001

Volume 29, Issue 4, September 2001

Volume 29, Issue 3, June 2001

Volume 29, Issue 2, May 2001

Execution-based prediction using speculative slices

Speculative precomputation

Dynamically allocating processor resources between nearby and distant ILP

Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors

Data prefetching by dependence graph precomputation

Concurrency, latency, or system overhead

Focusing processor policies via critical-path prediction

Automated design of finite state machine predictors for customized processors

Better exploration of region-level value locality with integrated computation reuse and value prediction

QoS provisioning in clusters

Locality vs. criticality

Dead-block prediction & dead-block correlating prefetchers

Code layout optimizations for transaction processing workloads

Exploring and exploiting wire-level pipelining in emerging technologies

A simple method for extracting models for protocol code

Removing architectural bottlenecks to the scalability of speculative parallelization

Power and energy reduction via pipeline balancing

Energy-effective issue logic

Variability in the execution of multimedia applications and implications for architecture

Rapid profiling via stratified sampling

Volume 29, Issue 1, March 2001

Code layout optimizations for transaction processing workloads

Content Provider	ACM Digital Library
Author	Barroso, Luiz André Ramirez, Alex Valero, Mateo Cohn, Robert Larriba-Pey, Josep Gharachorloo, Kourosh Lowney, P. Geoffrey
Abstract	Commercial applications such as databases and Web servers constitute the most important market segment for high-performance servers. Among these applications, on-line transaction processing (OLTP) workloads provide a challenging set of requirements for system designs since they often exhibit inefficient executions dominated by a large memory stall component. This behavior arises from large instruction and data footprints and high communication miss rates. A number of recent studies have characterized the behavior of commercial workloads and proposed architectural features to improve their performance. However, there has been little research on the impact of software and compiler-level optimizations for improving the behavior of such workloads.This paper provides a detailed study of profile-driven compiler optimizations to improve the code layout in commercial workloads with large instruction footprints. Our compiler algorithms are implemented in the context of Spike, an executable optimizer for the Alpha architecture. Our experiments use the Oracle commercial database engine running an OLTP workload, with results generated using both full system simulations and actual runs on Alpha multiprocessors. Our results show that code layout optimizations can provide a major improvement in the instruction cache behavior, providing a 55% to 65% reduction in the application misses for 64-128K caches. Our analysis shows that this improvement primarily arises from longer sequences of consecutively executed instructions and more reuse of cache lines before they are replaced. We also show that the majority of application instruction misses are caused by self-interference. However, code layout optimizations significantly reduce the amount of self-interference, thus elevating the relative importance of interference with operating system code. Finally, we show that better code layout can also provide substantial improvements in the behavior of other memory system components such as the instruction TLB and the unified second-level cache. The overall performance impact of our code layout optimizations is an improvement of 1.33 times in the execution time of our workload.
Starting Page	155
Ending Page	164
Page Count	10
File Format	PDF
ISSN	01635964
DOI	10.1145/384285.379260
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	29
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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