NDLI: Dynamically allocating processor resources between nearby and distant ILP

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Volume 29, Issue 5, December 2001

Volume 29, Issue 4, September 2001

Volume 29, Issue 3, June 2001

Volume 29, Issue 2, May 2001

Execution-based prediction using speculative slices

Speculative precomputation

Dynamically allocating processor resources between nearby and distant ILP

Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors

Data prefetching by dependence graph precomputation

Concurrency, latency, or system overhead

Focusing processor policies via critical-path prediction

Automated design of finite state machine predictors for customized processors

Better exploration of region-level value locality with integrated computation reuse and value prediction

QoS provisioning in clusters

Locality vs. criticality

Dead-block prediction & dead-block correlating prefetchers

Code layout optimizations for transaction processing workloads

Exploring and exploiting wire-level pipelining in emerging technologies

A simple method for extracting models for protocol code

Removing architectural bottlenecks to the scalability of speculative parallelization

Power and energy reduction via pipeline balancing

Energy-effective issue logic

Variability in the execution of multimedia applications and implications for architecture

Rapid profiling via stratified sampling

Volume 29, Issue 1, March 2001

Dynamically allocating processor resources between nearby and distant ILP

Content Provider	ACM Digital Library
Author	Dwarkadas, Sandhya Albonesi, David H. Balasubramonian, Rajeev
Abstract	Modern superscalar processors use wide instruction issue widths and out-of-order execution in order to increase instruction-level parallelism (ILP). Because instructions must be committed in order so as to guarantee precise exceptions, increasing ILP implies increasing the sizes of structures such as the register file, issue queue, and reorder buffer. Simultaneously, cycle time constraints limit the sizes of these structures, resulting in conflicting design requirements.In this paper, we present a novel microarchitecture designed to overcome the limitations of a register file size dictated by cycle time constraints. Available registers are dynamically allocated between the primary program thread and a future thread. The future thread executes instructions when the primary thread is limited by resource availability. The future thread is nor constrained by in order commit requirements. It is therefore able to examine a much larger instruction window and jump far ahead to execute ready instructions. Results are communicated back to the primary thread by warming up the register file, instruction cache, data cache, and instruction reuse buffer, and by resolving branch mispredicts early. The proposed microarchitecture is able to get on overall speedup of 1.17 over the base processor for our benchmark set, with speedups of up to 1.64.
Starting Page	26
Ending Page	37
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/384285.379249
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	29
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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