NDLI: Speculative execution for hiding memory latency

Content Provider	ACM Digital Library
Author	Pajuelo, Alex González, Antonio Valero, Mateo
Abstract	L2 misses are one of the main causes for stalling the activity in current and future microprocessors.In this paper we present a mechanism to speculatively execute independent instructions of L2-miss loads, even if no entry in the reorder buffer is available. The proposed mechanism generates future instances of instructions that are expected to be independent of the delinquent load. When these dynamic instructions are later fetched, they use the previously precomputed data and directly go to the commit stage without executing.The mechanism replicates strided loads found above the L2-miss load, that produce the data for the target independent instructions. Instructions following the L2-miss load will check if their source operands have been replicated. In this case, multiple speculative instances of them will also be generated.This mechanism is built on top of a superscalar processor with an aggressive prefetch scheme. Compared to this baseline, the mechanism obtains 21% of performance improvement.
Starting Page	49
Ending Page	56
Page Count	8
File Format	PDF
ISSN	01635964
DOI	10.1145/1101868.1101877
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	33
Issue Number	3
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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Speculative execution for hiding memory latency